FC106

Revision 1.2

16/32

September 98

4

Serial I/O Electrical Model

This simplified model is given for typical board simulation, within 15% precision. The

termination at the receiving end can be either internal or external, following Section 3.13.

Figure 4.1

Serial I/O electrical schematic diagram

50

Ω CONFIGURATI ON

75

Ω CONFIGURATION

R1

100

Ω

150

Ω

Rout

200

Ω

300

Ω

Rc

100

Ω if external termination

150

Ω if external termination

Rin

100

Ω if internal termination

150

Ω if internal termination

TO DESERIALIZER

0.01

µF(optional)

1.5K

Ω

Tr

R1

Tf

R1

Rout

1pF

1pF

Zc = 40

Ω

Td = 0.15nS

Zc = 40

Ω

Td = 0.15nS

Zc = 60

Ω

Td = 0.15nS

Zc = 60

Ω

Td = 0.15nS

0.01

µF(optional)

0.5pF

0.5pF

Rc

1.5K

Ω

1.5K

Ω

Tr = Tf = 0.2nS

1.5K

Ω

Simplified serial

transmitter model

Simplified QFP64

package model

Your board and/or

cable/connector model

Simplified QFP64

package model

Simplified serial

receiver model

PARAMETER VALUES

FOR TYP ICAL

SIMULATIO N

Rin