IS25LE02GG-RHLA2:P-TY datasheet(149/187 Pages) ISSI

部件名	IS25LE02GG-RHLA2:P-TY

功能描述	SERIAL FLASH MEMORY 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	187 Pages

Scroll/Zoom	100%

制造商	ISSI [Integrated Silicon Solution, Inc]

网页	http://www.issi.com

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149 / 187 page

IS25LE02GG

IS25WE02GG

Integrated Silicon Solution, Inc.- www.issi.com

149

Rev. A1

10/02/2025

8.52 WRITE DYB OPERATION (WRDYB, FBh or 4WRDYB, E1h)

Before the WRDYB/4WRDYB command can be accepted by the device, a standard Write Enable (06h) instruction

must previously have been executed for the device to accept Write DYB instruction (Status Register bit WEL must

equal 1).

• FBh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

• FBh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

• E1h is followed by a 4-byte address (A31-A0)

The WRDYB/4WRDYB command is entered by driving CE# low, followed by the instruction code, the 24-bit or 32-

bit address selecting location zero within the desired sector/block as above, then the data byte. The DYB Access

CE# must be driven high after the eighth bit of data has been latched in. As soon as CE# is driven high, the

WRDYB/4WRDYB operation is initiated.

Note: Data must be either 00h (protected) or FFh (unprotected).

Figure 8.115 Write DYB Sequence In SPI Mode (FBh [EXTADD=0], 3-byte address)

Instruction = FBh

CE #

SCK

...

Mode 3

Mode 0

3-byte Address

Data In

High Impedence

IS25LE02GG-RHLA2:P-TY 数据表(PDF) 149 Page - Integrated Silicon Solution, Inc