ADE7569 datasheet(45/144 Pages) AD

45 / 144 page

ADE7566/ADE7569/ADE7166/ADE7169

Rev. A | Page 45 of 144

Table 41. Interrupt Status 3 SFR (MIRQSTH, 0xDE)

Bit

Interrupt Flag

Description

RESET

Indicates the end of a reset (for both software and hardware reset).

Reserved.

WFSM

Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7).

PKI

Logic 1 indicates that current channel has exceeded the IPKLVL value

PKV

Logic 1 indicates that voltage channel has exceeded the VPKLVL value.

CYCEND

Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles.

ZXTO

Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles.

Logic 1 indicates detection of a zero crossing in the voltage channel.

Table 42. Interrupt Enable 1 SFR (MIRQENL, 0xD9)

Bit

Interrupt Enable Bit

Description

7 to 6

Reserved

Reserved.

FAULTSIGN1

When this bit is set, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052 core.

VARSIGN2

When this bit is set, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core.

APSIGN

When this bit is set, the APSIGN flag set creates a pending ADE interrupt to the 8052 core.

VANOLOAD

When this bit is set, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core.

RNOLOAD2

When this bit is set, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core.

APNOLOAD

When this bit is set, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core.

1 This function is not available in the ADE7566 and ADE7569.

2 This function is not available in the ADE7566 and ADE7166.

Table 43. Interrupt Enable 2 SFR (MIRQENM, 0xDA)

Bit

Interrupt Enable Bit

Description

CF2

When this bit is set, a CF2 pulse creates a pending ADE interrupt to the 8052 core.

CF1

When this bit is set, a CF1 pulse creates a pending ADE interrupt to the 8052 core.

VAEOF

When this bit is set, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.

REOF1

When this bit is set, the REOF flag set creates a pending ADE interrupt to the 8052 core.

AEOF

When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core.

VAEHF

When this bit is set, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.

REHF1

When this bit is set, the REHF flag set creates a pending ADE interrupt to the 8052 core.

AEHF

When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core.

1 This function is not available in the ADE7566 and ADE7166.

ADE7569 数据表(PDF) 45 Page - Analog Devices

ADE7569 数据表(HTML) 45 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ADE7569 数据表(PDF) 45 Page - Analog Devices

ADE7569 数据表(HTML) 45 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载