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ADE7569 数据表(PDF) 14 Page - Analog Devices |
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ADE7569 数据表(HTML) 14 Page - Analog Devices |
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14 / 144 page  ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 14 of 144 Table 10. SPI Slave Mode Timing (SPICPHA = 0) Parameters Parameter Description Min Typ Max Unit tSS SS 145 ns to SCLK edge tSL SCLK low pulse width 6 × tCORE1 ns tSH SCLK high pulse width 6 × tCORE1 ns tDAV Data output valid after SCLK edge 25 ns tDSU Data input setup time before SCLK edge 0 ns tDHD Data input hold time after SCLK edge 2 × tCORE1+ 0.5 μs μs tDF Data output fall time 19 ns tDR Data output rise time 19 ns tSR SCLK rise time 19 ns tSF SCLK fall time 19 ns tDOSS Data output valid after SS 0 edge ns tSFS SS 0 ns high after SCLK edge 1 tCORE depends on the clock divider or CD bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz. MSB MOSI BITS [6:1] tDHD tDSU LSB IN BITS [6:1] LSB tDR tDF tDAV MISO tSR tSF tSFS tSS SCLK (SPICPOL = 1) SCLK (SPICPOL = 0) SS tSH tSL tDOSS MSB IN Figure 8. SPI Slave Mode Timing (SPICPHA = 0) |
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