ADE7569 datasheet(28/144 Pages) AD

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ADE7566/ADE7569/ADE7166/ADE7169

Rev. A | Page 28 of 144

The battery switchover functionality provided by the

ADE7566/ADE7569/ADE7166/ADE7169 allows a seamless

transition from VDD to VBAT. An automatic battery switchover

option ensures a stable power supply to the ADE7566/

ADE7569/ADE7166/ADE7169, as long as the external battery

voltage is above 2.75 V. It allows continuous code execution

even while the internal power supply is switching from VDD to

VBAT and back. Note that the energy metering ADCs are not

available when VBAT is being used for VSWOUT.

POWER SUPPLY ARCHITECTURE

Each ADE7566/ADE7569/ADE7166/ADE7169 has two power

supply inputs, VDD and VBAT, and require only a single 3.3 V

power supply at VDD for full operation. A battery backup, or

secondary power supply, with a maximum of 3.7 V can be

connected to the VBAT input. Internally, the ADE7566/ADE7569/

ADE7166/ADE7169 connect VDD or VBAT to VSWOUT, which is used

to derive power for the ADE7566/ADE7569/ ADE7166/ADE7169

circuitry. The VSWOUT output pin reflects the voltage at the

internal power supply (VSWOUT) and has a maximum output

current of 6 mA. This pin can also be used to power a limited

number of peripheral components. The 2.5 V analog supply (VINTA)

and the 2.5 V supply for the core logic (VINTD) are derived by on-

chip linear regulators from VSWOUT.

Power supply monitor (PSM) interrupts can be enabled to

indicate when battery switchover occurs and when the VDD

power supply is restored (see the Power Supply Monitor

Interrupt (PSM) section.)

Figure 31 shows the power

supply architecture of ADE7566/ADE7569/ADE7166/ADE7169.

VDD to VBAT

The following three events switch the internal power supply

(VSWOUT) from VDD to VBAT:

The ADE7566/ADE7569/ADE7166/ADE7169 provide

automatic battery switchover between VDD and VBAT based on

the voltage level detected at VDD or VDCIN. Additionally, the

BCTRL input can be used to trigger a battery switchover. The

conditions for switching VSWOUT from VDD to VBAT and back to

VDD are described in the

•

VDCIN < 1.2 V. When VDCIN falls below 1.2 V, VSWOUT switches

from VDD to VBAT. This event is enabled when the

BATPRG[1:0] bits in the Battery Switchover Configuration

SFR (BATPR, 0xF5) = 0b01. Setting these bits disables

switchover based on VDCIN. Battery switchover on low VDCIN is

disabled by default.

Battery Switchover section. VDCIN is an

input pin that can be connected to a 0 V to 3.3 V dc signal. This

input is intended for power supply supervisory purposes and

does not provide power to the ADE7566/ADE7569/ADE7166/

ADE7169 circuitry (see the

•

VDD < 2.75 V. When VDD falls below 2.75 V, VSWOUT switches

from VDD to VBAT. This event is enabled when BATPRG[1:0] in

the BATPR SRF are cleared.

Battery Switchover section).

POWER SUPPLY

MANAGEMENT

LDO

VINTD

LDO

VINTA

ADC

VSW

ADC

SCRATCHPAD

LCD

RTC

TEMPERATURE ADC

3.3V

MCU

ADE

SPI/I2C

UART

2.5V

VDCIN VDD VBAT

VSWOUT

BCTRL

•

Falling edge on BCTRL. When the battery control pin,

BCTRL, goes low, VSWOUT switches from VDD to VBAT. This

external switchover signal can trigger a switchover to VBAT

at any time. Setting bits INT1PRG[4:2] to 0bx01 in the

Interrupt Pins Configuration SFR (INTPR, 0xFF) enables

the battery control pin (see Table 16).

Switching from VBAT to VDD

To switch VSWOUT from VBAT to VDD, all of the following events

that are enabled to force battery switchover must be false:

•

VDCIN < 1.2 V and VDD < 2.75 V enabled. If the low VDCIN

condition is enabled, VSWOUT switches to VDD after VDCIN

remains above 1.2 V and VDD remains above 2.75 V.

Figure 31. Power Supply Architecture

BATTERY SWITCHOVER

The ADE7566/ADE7569/ADE7166/ADE7169 monitor VDD, VBAT,

and VDCIN. Automatic battery switchover from VDD to VBAT can be

configured based on the status of VDD, VDCIN, or the BCTRL pin.

Battery switchover is enabled by default. Setting Bit 1 in the

Battery Switchover Configuration SFR (BATPR, 0xF5) disables

battery switchover so that VDD is always connected to VSWOUT

(see

•

VDD < 2.75 V enabled. VSWOUT switches back to VDD after

VDD remains above 2.75 V.

•

BCTRL enabled. VSWOUT switches back to VDD after BCTRL

is high, and the first or second bullet point is satisfied.

Table 18). The source of VSWOUT is indicated by Bit 6 in the

Peripheral Configuration SFR (PERIPH, 0xF4), which is

described in Table 19. Bit 6 is set when VSWOUT is connected to

VDD and cleared when VSWOUT is connected to VBAT.

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