L4969

10/35

1.2

Power-Up, Initialization and Sleep mode transitions

The following state-diagram illustrates the possible mode transitions inside the device.

As a prerequisite, a SPI-connection to the uC with the correct CRC-algorythms is required.

During the debug phase the NRES line can be forced high externally (connect to V1) to deactivate the startup

failure mechanis keeping V1 will alive.

Figure 3.

STARTUP

V1 active

V2, V3, CAN off

t=320ms

STARTUP

FAILURE

t=1ms

(fail ++)

fail = 7

FORCED SLEEP

WAKEUP

V1 off

V1 Low

RESET low

WDC-ACK

WDC-ACK

WINDOW

WATCHDOG

REFRESH

WDC-OK

WDC-FAIL

NORMAL MODE

WINDOW WDC

ACTIVE

WND SET

NORMAL MODE

WINDOW WDC

DISABLED

TIMER

ACTIVE

WDEN SET

TIMEOUT | WDC-ACK

NRES Low

Programmed

DISAR

SET

DISAR

SET

WAKEUP

WAKEUP&V1_UV

Writing to the WDC-

register

(WDC-ACK)

the NORMAL STATE is

entered.

A missing ACK within 320ms will

initiate a STARTUP FAILURE

phase (RESET low).

If no WDC-ACK is received within

seven retrials the voltage regulator

V1 will be turned off by entering the

FORCED SLEEP state.

Dependig on the value from the last

WDC-ACK, another one has to be

written within the specified time frame

(SWDC[1:0]). A failure will activate

the STARTUP STATE

The Window supervision can temporarily be de-

activated for the time programmed during the

last WDC-ACK (WDT[3:0]). Upon rewriting

(WDC-ACK) or expiry of the timer, the NORMAL

STATE is reentered.

If during the last WDC-ACK WND has been set (after releasing

write lock, see description of Watchdog Control Register) the Win-

dow watchdog is deactivated, and no uC supervision is active.

TIMER

ACTIVE

WDEN SET

(restart by double

WDC-ACK & WDEN)

TIMEOUT | WDC-ACK

Here the timer can be used to

generate time events (i.e.

wakeup uC from stop)

After POR, V1 up or externally forced reset

through low NRES, the STARTUP STATE is

entered

The forced sleep mode is left upon wakeup through either CAN or edge on

WAKE. Applying a permanent wakeup (i.e. both CAN-lines dominant) pre-

vents V1 from being turned off (can be used during System debugging)

Setting DISAR (see Voltage Regulator Control Register) Voltage regulator V1 is

turned off, and the output voltage is decreasing depending on the external load

and blocking capacitor.

Note, that during this transition no Reset will be generated (due to Debugmode).

Upon wakeup howewer NRES will be pulled low, if V1was below the programma-

ble reset threshold (V1_UV).

Forcing NRES high externally, fail will not be incremented (Emulation)

(restart by double

WDC-ACK & WDEN)

WAKEUP

WDC-ACK

WDEN SET

&

SLEEP

V1 OFF

No Reset

WAKEUP

&V1_UV

No Reset