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L4969 数据表(PDF) 15 Page - STMicroelectronics

部件名 L4969
功能描述  SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT LOW SPEED CAN-TRANSCEIVER
PDF  35 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

L4969 数据表(HTML) 15 Page - STMicroelectronics

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L4969
In case of single wire communication via CANH the signal to noise ratio is low. Detecting the local ground shift
can be used as an additional indicator on the current signal quality. The information of the integrated ground
shift detector will be refreshed upon every falling edge on TX and can be read from the CAN Transceiver Status
Register (CTSR).
It will be set, if V(CANH) < -1V, reset if V(CANH > -1V) at the falling edge of TX.
1.9
Thermal Protection
The device features three independent thermal warning circuits which monitor the temperature of the V1 output,
the V2 output and the CAN_H and CAN_L drivers together with voltage regulator V3. Each circuit sets a sepa-
rate overtemperature flag in a register which is read and writable by the serial interface. The overtemperature
flags cause an interrupt to the
µC. The µC is able to switch V1, V2 and CAN drivers on and off through dedicated
enable registers. To enhance system security following strategy is chosen for thermal warning and shutdown:
– 3 independent warning flags are set at 140°C for V1, V2 and V3 /CAN-Transceiver
– at 170°C V2 and V3 switched off
– at 200°C V1 is switched off
– V2 and V3 can be switched on again through the
µC
– V1 can be switched on again at wake-up (Watchdog wake-up, CAN wake-up, external wake-up)
Note, that if no wakeup source is set for V1 a 1sec watchdog timeout will be established to enable a proper retry
cycle.
1.10 Serial Interface (SPI)
A standard serial peripheral interface (SPI) is implemented to allow access to the internal registers of the L4969.
A total of 12 Registers with different datalengths can be directly read from or written to, providing the requested
address at the beginning of a dataframe. Upon every access to this interface, the content of the register currently
accessed is shifted out via SOUT. All operations are performed on the rising edge of SCLK.
If a frame is not completed, the interface is automatically reset after 1.5ms of SCLK idle time (auto timeout de-
tection). If a message is corrupted (additional or missing SCLK pulses), the application software can detect this
by evaluating the returned value of the crc and force a communication gap of min 1.5ms to allow communicva-
tion recovery. A corruption can be caused during startup of the uC and SPI initialization. The application should
then wait at least 1.5ms after SPI init prior to starting the communication.
The dataframe format used described on the next page:



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