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L4969

2.3

ADR 2: GPTR Global Parameter and Test Register

Figure 13.

2.4

ADR 3: RCADJ RC-Oscillator Adjust register

Figure 14.

During normal operation the

with 50% duty cycle. Note, that all other pending interrupts have to be cleared before.

After the XTAL driven timer of the

CG1 and CG0 have to be set to ‘10’ to disable the adjustment cycle on NINT. From the deviation calculated by

the

to ‘00’ or ‘11’. (‘11’ can be used to indicate that calibration has already been performed).

Note, that overwriting this register is only valid, if the cycle measurement was started and terminated properly.

This can be tested by evaluating PGEN either prior to or during correction (Read back via SOUT).

Note also, that any write to the WDC register will reset the timer and thus reset the phase of the testcycle. There-

fore a cyclic access to the window watchdog during the pulsewidth measurement has to be avoided and the

timer watchdog to be used instead (i.e. 1sec)

RES

RES

RES

RES

D7

D0

TM1

TM0

TMUX

TEN

This register is to be used for testpurpose only, all bits have to remain ‘zero’

CG1

CG0

PGEN

ADJ4

ADJ3

ADJ2

ADJ1

ADJ0

D7

D0

00: No request (Adjustment disabled)

01: 2.5ms low cycle on NINT (repetitive)

10: Finish cycle measurement

11: No request (Adjustment disabled)

Test cycle request

A low pulse on NINT

for a fixed period

of time can be requested

for XTAL synchronization

Program enable (read only)

Bit will be set after 'Finish cycle measurement',

and reset after register write

1: +16%

0: 0%

0: 0%

1: -8%

0: 0%

1: -4%

0: 0%

1: -2%

0: 0%

1: -1%

RC Oscillator

Frequency Adjust

default value 10000

Note, that programming

is only enabled with PGEN set

99AT0022