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L4969

2.8

ADR7: CTSR CAN Transceiver Status Register

Figure 23.

Note, that this register is read only and only provides the unlatched information on current buserrors.

D11

D0

RES

RES

RES

GSH

EI_V

EII_IX

EIII

EIV

EVIII

EVII

EVI

EX

Reserved bits (‘RES’) are always read as ‘0’

CANH < -1V

at falling edge TX

TX permanent

dominant detected

CANH permanent

dominant detected

(TXD = ‘0’, t > 1.3ms)

(CANH > 1.8V, t > 1.3ms)

Short circuit CANH to CANL detected

(CANH - CANL > -3.25V, t > 1.3ms)

CANL short

circuit to VS

detected

(CANL > 7.2V,

t > 32us)

CANL permanent

dominant detected

(CANL < 3.1V,

t > 1.3ms)

CANH short

circuit to VS

detected

(CANH > 7.2V,

t > 32us)

Single wire

communication

detected

(edge count

difference > 3)

EI_V : CANH off

EII_IX : CANL off