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L4969 数据表(PDF) 13 Page - STMicroelectronics

部件名 L4969
功能描述  SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT LOW SPEED CAN-TRANSCEIVER
PDF  35 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

L4969 数据表(HTML) 13 Page - STMicroelectronics

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L4969
1.4
Oscillator
A low power oscillator provides an internal clock. In sleep mode (Watchdog active) the output frequency is
250kHz, if the Watchdog function is not requested, the internal Oscillator is switched off.
In standby and operating mode the oscillator is running at 1MHz, and can be calibrated in a range from -16% to
+16% using the
µC-XTAL as a reference.
1.5
WatchdL4969og
A triple function programmable watchdog is integrated to perform the following tasks:
– Wakeup Watchdog:
When in sleep or standby mode the watchdog can generate a wakeup condition after a programma-
ble period of time ranging from 80ms up to 45 minutes
– Startup Watchdog:
Upon V1 power-up or
µC failure during SPI supervision (see SW-Watchdog) a reset pulse is gener-
ated periodically every 320ms for 2.5ms until activity of the
µC is detected (SPI sequence) or no ac-
knowledge is received within 7 cycles (2.2sec). In this condition the device is forced into Sleep mode
until a Wakeup is detected and a startup cycle is reinitialized.
– Window Watchdog:
After passing the startup sequence, this watchdog request an acknowledge by the
µC via the SPI
within a programmable timing frame, ranging from 2.5 ... 5ms up to 20 ... 40ms. Upon a missing or
misplaced acknowledge the Startup Watchdog is initialized.
1.6
Reset
1.6.1 Power-on Reset
Upon Power-on (VS > 3.5V), the internal reset forces the device into a predefined power-on state (see 1.1):
Standby #3:V1 on V2 off V3 off,CAN-Standby mode, ID-Filter disabled, Startup Watchdog active
With VS below 5V the regulator V1 will follow VS with minimum drop. The
µC retrieves a reset if V1 is dropping
below a programmable voltage level of either 4.5V (default) or 4.0V. The programmed state of the L4969 re-
mains unchanged. The act. low Resetpulse duration is fixed internally by an open-drain output stage to 1ms.
However, this time can be externally extended by an additional capacitance connect between NRESET and
GROUND which is then charged by the internal pull-up of typ. 120K. Depending on the Reset-Input-Threshold
of the uC (UTR), the reqired Capacitance for a typical tD can be calculated as follows:
CEXT = -tD / (120E3 ln(1-UTR/V1))).
To obtain a reset-pulse duration of tD = 50ms with UTR/V1 = 0.5, a Capacitance of CEXT= -50E-3 / (120E3 ln
0.5) = 600nF is required.
Figure 4.
1.6.2
Undervoltage Reset
Upon detection of a V1 voltage level below a programmable voltage level of either 4.5V (default) or 4.0V,the
NRES-pin is pulled low. Since this undervoltage detection is additionally sampled periodically every ms, the
NRES low time will be extended by up to 1 ms if V1 was low (V1UV) at the sampling point (see below).
V1
120K
NRES
CEXT
to Reset Input of uC



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