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L4969 数据表(PDF) 19 Page - STMicroelectronics

部件名 L4969
功能描述  SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT LOW SPEED CAN-TRANSCEIVER
PDF  35 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

L4969 数据表(HTML) 19 Page - STMicroelectronics

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L4969
2
CONTROL AND STATUS REGISTERS
The functionality of the device can be observed and controlled through a set of registers which are read and
writable by the serial interface.
2.1
ADR 0: VRCR Voltage Regulator Control Register
Figure 11.
Note, that when using the Undervoltage-detection, EUV2 and EUV3 have to be activated AFTER V2 or V3 have
been turned on and settled (t > 1ms). Otherwise unwanted undervoltage can be detectected during turn on of
the corresponding voltage regulator.
TRC
Disable all Regulators (Go to Sleep)
Enable Regulator #3 .
V3 will be activated by either setting ENV3 or
upon enabling of the CAN Lineinterface
Enable Regulator #2.
Enable Regulator #2 tracking option
RES
to have V2 following V1 with constant offset
RTC0
Set reset threshold value to 4.0V
Default value is ‘0’ (4.5V)
EUV2
EUV3
ENV3
ENV2
DISAR
Has to be
Default value is ‘0’ (disabled)
Default value is ‘0’ (disabled)
This bit will be automatically reset upon
Overtemperature from CANIF or Regulator #3
Default value is ‘0’ (disabled)
This bit will be automatically reset upon
Overtemperature at Regulator #2.
D7
D0
DISAR
V1
V3
(DISAR & ENV3 |
ACT) & TSDV3
TRC
V2
DISAR & ENV2
Note, that at least one Wakeup Source
to enable access.
This bit will be automatically set upon
the system failures Overtemperature V1
Enable undervoltage
detection on
Regulator #2 and #3
REF
(see note below)
Note, that due to the large initial charging current of the output capacitors,
the activation of V2 AND V3 within the same command is not recommended
written as ‘0’.
without a pending wakeup is required
or watchdog startup failure.
DISAR will be cleared upon a valid
wakeup signal which is either defined
in GIEN or is forced to WAKE or CAN
after a system failure
V3 will be activated upon VRCR.ENV3 or
CCTR.ACT without pending thermal shutdown
Note, that no reset will be generated
from low V1 during Sleep mode transition
The Reset line has to be forced low
externally, or through a window failure
also leaving ENV2 or ENV3 set when setting DISAR can therefor not be
recommended (after wakeup V1 AND V2 or V3 would be turned on)



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