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STM32L4P5CE 数据表(PDF) 255 Page - STMicroelectronics |
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STM32L4P5CE 数据表(HTML) 255 Page - STMicroelectronics |
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255 / 311 page  DS12903 Rev 2 255/311 STM32L4P5xx Electrical characteristics 277 In all timing tables, the THCLK is the HCLK clock period. • For 2.7 V ≤ VDD ≤ 3.6 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and 54 MHz for CLKDIV = 0x0 at CL = 30 pF (on FMC_CLK). • For 1.71 V ≤ VDD ≤ 2.7 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and 32 MHz for CLKDIV = 0x0 at CL= 20 pF (on FMC_CLK). Figure 52. Synchronous multiplexed NOR/PSRAM read timings FMC_CLK FMC_NEx FMC_NADV FMC_A[25:16] FMC_NOE FMC_AD[15:0] AD[15:0] D1 D2 FMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKH-NExH) t d(CLKL-NADVL) td(CLKL-AV) td(CLKL-NADVH) td(CLKH-AIV) td(CLKL-NOEL) td(CLKH-NOEH) td(CLKL-ADV) td(CLKL-ADIV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) MS32757V1 |
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