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STM32L4P5CE 数据表(PDF) 271 Page - STMicroelectronics |
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STM32L4P5CE 数据表(HTML) 271 Page - STMicroelectronics |
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271 / 311 page ![]() DS12903 Rev 2 271/311 STM32L4P5xx Electrical characteristics 277 Table 119. PSSI receive characteristics(1) 1. Guaranteed by characterization results. Symbol Parameter Conditions Min Max Unit - Frequency ratio PSSI_PDCK/fHCLK -- 0.4 - PSSI_PDCK PSSI Clock input 1.71<VDD<3.6 Voltage Range V1 -48 MHz 1.71<VDD<3.6 Voltage Range V2 -10 Dpixel PSSI Clock input duty cycle - 30 70 % tsu(DATA) Data input setup time 1.71<VDD<3.6 Voltage Range V1 4.5 - ns 1.71<VDD<3.6 Voltage Range V2 6.5 - th(DATA) Data input hold time 1.71<VDD<3.6 Voltage Range V1 0.5 - 1.71<VDD<3.6 Voltage Range V2 0.5 - tsu((DE) DE input setup time 1.71<VDD<3.6 Voltage Range V1 1.5 - 1.71<VDD<3.6 Voltage Range V2 2- th(DE) DE input hold time 1.71<VDD<3.6 Voltage Range V1 0.5 - 1.71<VDD<3.6 Voltage Range V2 0.5 - tov(RDY) RDY output valid time 1.71<VDD<3.6 Voltage Range V1 -18 1.71<VDD<3.6 Voltage Range V2 - 21.5 toh(RDY) RDY output hold time 1.71<VDD<3.6 Voltage Range V1 7- 1.71<VDD<3.6 Voltage Range V2 10.5 - |
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