STM32F427AI datasheet(71/240 Pages) STMICROELECTRONICS

71 / 240 page

DS9405 Rev 12

71/240

STM32F427xx STM32F429xx

Pinouts and pin description

98 142

170 A10 201

PE1

I/O FT

UART8_Tx,

FMC_NBL1, DCMI_D3,

EVENTOUT

202

VSS

S-

143

171 A11 203

PDR_ON

100 144

172 D7 204

VDD

S-

173

205

PI4

I/O FT

TIM8_BKIN,

FMC_NBL2, DCMI_D5,

LCD_B4, EVENTOUT

174

206

PI5

I/O FT

TIM8_CH1,

FMC_NBL3,

DCMI_VSYNC,

LCD_B5, EVENTOUT

175

207

PI6

I/O FT

TIM8_CH2, FMC_D28,

DCMI_D6, LCD_B6,

EVENTOUT

176

208

PI7

I/O FT

TIM8_CH3, FMC_D29,

DCMI_D7, LCD_B7,

EVENTOUT

1. Function availability depends on the chosen device.

2. On the UFBGA176 package, the balls F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10,

K6, K7, K8, K9, and K10 are connected to VSS. Their purpose is heat dissipation and package mechanical stability

3. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the

output data register to avoid extra current consumption in low-power modes.

4. PC13, PC14, PC15, and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF.

- These I/Os must not be used as a current source (for example, to drive an LED).

5. The main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even

after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the

RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website:

www.st.com.

6. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0, and PH1).

7. If the device is delivered in a WLCSP143, UFBGA169, UFBGA176, LQFP176 or TFBGA216 package, and the

BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active

low).

8. PI0 and PI1 cannot be used for I2S2 full-duplex mode.

9. The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3.

Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)

Pin number

Pin name

(function

after reset)(1)

Alternate functions

Additional

functions

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