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STM32F427AI 数据表(PDF) 20 Page - STMicroelectronics |
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STM32F427AI 数据表(HTML) 20 Page - STMicroelectronics |
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20 / 240 page  Description STM32F427xx STM32F429xx 20/240 DS9405 Rev 12 Figure 4. STM32F427xx and STM32F429xx block diagram 1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 2. The LCD-TFT is available only on STM32F429xx devices. MSv30420V5.svg GPIO PORT A AHB/APB2 EXT IT. WKUP 168 AF PA[15:0] TIM1 / PWM 4 compl. chan. (TIM1_CH1[1:4]N), 4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF USART1 RX, TX, CK, CTS, RTS as AF SPI1 MOSI, MISO, SCK, NSS as AF 8 analog inputs common to the 3 ADCs VDDREF_ADC UART4 MOSI/SD, MISO/SD_ext, SCK/CK NSS/WS, MCK as AF SP3/I2S3 TX, RX bxCAN2 DAC1_OUT as AF ITF WWDG 4 KB BKPSRAM RTC_AF1 OSC32_IN OSC32_OUT VDDA, VSSA NRST smcard irDA 16b SDIO / MMC D[7:0] CMD, CK as AF VBAT = 1.65 to 3.6 V DMA2 SCL, SDA, SMBA as AF I2C3/SMBUS JTAG & SW Arm Cortex-M4 180 MHz NVIC ETM MPU TRACECLK TRACED[3:0] Ethernet MAC 10/100 DMA/ FIFO MII or RMII as AF MDIO as AF USB OTG HS DP, DM ULPI:CK, D[7:0], DIR, STP, NXT ID, VBUS, SOF DMA2 8 Streams FIFO SRAM 112 KB CLK, NE [3:0], A[23:0], D[31:0], NOEN, NWEN, NBL[3:0], SDCLKE[1:0], SDNE[1:0], SDNWE, NL NWAIT/NIORD, NREG, CD INTR RNG Camera interface HSYNC, VSYNC PUIXCLK, D[13:0] USB OTG FS DP DM ID, VBUS, SOF AHB1 180 MHz US AR T 2 M B p s Temperature sensor ADC1 ADC2 ADC3 IF IF @VDDA @VDDA POR/PDR BOR Supply supervision @V DDA PVD Int POR reset XTAL 32 kHz MAN A G T RTC RC HS RC L S Standby interface IWDG @V BAT @V DDA @V DD AWU Reset & clock control PLL1,2,3 VDD = 1.8 to 3.6 V VSS VCAP1, VCAP2 Voltage regulator 3.3 to 1.2 V VDD Power managmt @V DD RTC_AF1 Backup register TIM14 TIM9 2 channels as AF DAC1 DAC2 1MB Flash External memory controller (FMC) SRAM, SDRAM, PSRAM, NOR Flash, PC Card, NAND Flash TIM6 TIM7 TIM2 TIM3 TIM4 TIM5 TIM12 D-BUS FPU SRAM 16 KB CCM data RAM 64 KB AHB3 AHB2 180 MHz NJTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO I-BUS S-BUS DMA/ FIFO DMA1 8 Streams FIFO PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] PH[15:0] PI[15:0] GPIO PORT B GPIO PORT C GPIO PORT D GPIO PORT E GPIO PORT F GPIO PORT G GPIO PORT H GPIO PORT I TIM8 / PWM 16b 16b TIM10 16b TIM11 16b smcard irDA USART6 4 compl. chan.(TIM8_CH1[1:4]N), 4 chan. (TIM8_CH1[1:4], ETR, BKIN as AF 1 channel as AF 1 channel as AF RX, TX, CK, CTS, RTS as AF 8 analog inputs common to the ADC1 & 2 8 analog inputs for ADC3 DAC2_OUT as AF 16b 16b bxCAN1 I2C2/SMBUS I2C1/SMBUS SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF SP2/I2S2 MOSI/SD, MISO/SD_ext, SCK/CK NSS/WS, MCK as AF TX, RX RX, TX as AF RX, TX as AF RX, TX as AF CTS, RTS as AF RX, TX as AF CTS, RTS as AF 1 channel as AF UART5 USART3 USART2 smcard irDA smcard irDA 16b 16b 16b 1 channel as AF TIM13 2 channels as AF 32b 16b 16b 32b 4 channels 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF DMA1 AHB/APB1 OSC_IN OSC_OUT XTAL OSC 4- 26MHz SPI4 SCK, NSS as AF SPI5 SCK, NSS as AF MOSI, MISO, MOSI, MISO, SPI6 SCK, NSS as AF MOSI, MISO, RX, TX as AF UART7 RX, TX as AF UART8 SRAM 64 KB 1MB Flash FIFO LCD-TFT FIFO PJ[15:0] GPIO PORT J PK[7:0] GPIO PORT K SAI1 SD, SCK, FS, MCLK as AF NRAS, NCAS, NADV RTC_50HZ LCD_R[7:0], LCD_G[7:0], LCD_B[7:0], LCD_HSYNC, LCD_VSYNC, LCD_DE, LCD_CLK CHROM-ART DMA2D |
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