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STM32F427AI 数据表(PDF) 31 Page - STMicroelectronics |
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STM32F427AI 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 240 page ![]() DS9405 Rev 12 31/240 STM32F427xx STM32F429xx Functional overview 44 Figure 9. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 10. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 1. This figure is valid whatever the internal reset mode (ON or OFF). ai18491f VDD time Min V12 PDR = 1.7 V or 1.8 V VCAP_1 / VCAP_2 V12 NRST time VDD time Min V12 VCAP_1 / VCAP_2 V12 PA0 asserted externally NRST time ai18492e PDR = 1.7 V or 1.8 V |
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