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STM32F427AI 数据表(PDF) 153 Page - STMicroelectronics |
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STM32F427AI 数据表(HTML) 153 Page - STMicroelectronics |
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153 / 240 page  DS9405 Rev 12 153/240 STM32F427xx STM32F429xx Electrical characteristics 197 Figure 46. ULPI timing diagram Table 70. USB HS clock timing parameters(1) 1. Specified by design. Symbol Parameter Min Typ Max Unit fHCLK value to guarantee proper operation of USB HS interface 30 - - MHz FSTART_8BIT Frequency (first transition) 8-bit ±10% 54 60 66 MHz FSTEADY Frequency (steady state) ±500 ppm 59.97 60 60.03 MHz DSTART_8BIT Duty cycle (first transition) 8-bit ±10% 40 50 60 % DSTEADY Duty cycle (steady state) ±500 ppm 49.975 50 50.025 % tSTEADY Time to reach the steady state frequency and duty cycle after the first transition -- 1.4 ms tSTART_DEV Clock startup time after the de-assertion of SuspendM Peripheral - - 5.6 ms tSTART_HOST Host - - - tPREP PHY preparation time after the first transition of the input clock -- - µs Clock Control In (ULPI_DIR, ULPI_NXT) data In (8-bit) Control out (ULPI_STP) data out (8-bit) tDD tDC tHD tSD tHC tSC ai17361c tDC |
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