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STM32F427AI 数据表(PDF) 159 Page - STMicroelectronics |
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STM32F427AI 数据表(HTML) 159 Page - STMicroelectronics |
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159 / 240 page ![]() DS9405 Rev 12 159/240 STM32F427xx STM32F429xx Electrical characteristics 197 Equation 1: RAIN max formula The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. fS(2) Sampling rate (fADC = 30 MHz, and tS = 3 ADC cycles) 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps IVREF+(2) ADC VREF DC current consumption in conversion mode - - 300 500 µA IVDDA(2) ADC VDDA DC current consumption in conversion mode -- 1.6 1.8 mA 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). 2. Evaluated by characterization results. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. RADC maximum value is given for VDD=1.7 V, and a minimum value for VDD=3.3 V. 5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 75. Table 75. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Table 76. ADC static accuracy at fADC = 18 MHz Symbol Parameter Test conditions Typ Max(1) 1. Evaluated by characterization - not tested in production results. Unit ET Total unadjusted error fADC =18 MHz VDDA = 1.7 to 3.6 V VREF = 1.7 to 3.6 V VDDA − VREF < 1.2 V ±3 ±4 LSB EO Offset error ±2 ±3 EG Gain error ±1 ±3 ED Differential linearity error ±1 ±2 EL Integral linearity error ±2 ±3 RAIN k0.5 – () fADC CADC 2 N 2 + () ln × × ---------------------------------------------------------------- RADC – = |
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