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M36DR232 数据表(PDF) 2 Page - STMicroelectronics |
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M36DR232 数据表(HTML) 2 Page - STMicroelectronics |
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2 / 46 page ![]() M36D232A, M36DR232B 2/46 DESCRIPTION The M36DR232 is a multichip memory device con- taining a 32 Mbit boot block Flash memory and a 4Mbit of SRAM. Thedeviceis offered in aStacked LFBGA66 (0.8 mm pitch) package. The two components are distinguished by use with three chip enable inputs: EF for the Flash memory and, E1S and E2S for the SRAM. The two compo- nents are also separately power supplied and grounded. Figure 2. Logic Diagram Table 1. Signal Names AI05440 21 A0-A20 EF DQ0-DQ15 M36DR232A M36DR232B GF VSSF 16 WF RPF WPF E1S E2S GS WS UBS LBS VSSS VDDF VPPF VDDS A0-A16 Address Inputs A17-A20 Address Inputs for Flash Chip only DQ0-DQ15 Data Input/Output VDDF Flash Power Supply VPPF Flash Optional Supply Voltage for Fast Program & Erase VSSF Flash Ground VDDS SRAM Power Supply VSSS SRAM Ground NC Not Connected Internally Flash control functions EF Chip Enable input GF Output Enable input WF Write Enable input RPF Reset input WPF Write Protect input SRAM control functions E1S, E2S Chip Enable input GS Output Enable input WS Write Enable input UBS Upper Byte Enable input LBS Lower Byte Enable input |
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