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M36DR232 数据表(PDF) 35 Page - STMicroelectronics |
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M36DR232 数据表(HTML) 35 Page - STMicroelectronics |
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35 / 46 page ![]() 35/46 M36D232A, M36DR232B Table 31. SRAM Read AC Characteristics (TA = –40 to 85°C; VDDS = 1.65V to 2.2V) Note: 1. Sampled only. Not 100% tested. Figure 16. SRAM Read Mode AC Waveforms, Address Controlled with UBS =LBS =VIL Note: E1S = Low, E2S = High, GS =Low, WS = High. Symbol Alt Parameter SRAM Unit Min Max tAVAV tRC Read Cycle Time 70 ns tAVQV tAA Address Valid to Output Valid 70 ns tAXQX tOH Address Transition to Output Transition 10 ns tBHQZ tBHZ UBS, LBS Disable to Hi-Z Output 25 ns tBLQV tBA UBS, LBS Access Time 70 ns tBLQX tBLZ UBS, LBS Enable to Low-Z Output 5 ns tE1HQZ tHZ1 Chip Enable 1 High to Output Hi-Z 25 ns tE1LQV tCO1 Chip Enable 1 Low to Output Valid 70 ns tE1LQX tLZ1 Chip Enable 1 Low to Output Transition 10 ns tE2HQV tCO2 Chip Enable 2 High to Output Valid 70 ns tE2HQX tLZ2 Chip Enable 2 High to Output Transition 10 ns tE2LQZ tHZ2 Chip Enable 2 Low to Output Hi-Z 25 ns tGHQZ tOHZ Output Enable High to Output Hi-Z 25 ns tGLQV tOE Output Enable Low to Output Valid 35 ns tGLQX tOLZ Output Enable Low to Output Transition 5 ns tPD (1) Chip Enable 1 High or Chip Enable 2 Low to Power Down 70 ns tPU (1) Chip Enable 1 Low or Chip Enable 2 High to Power Up 0 ns AI04115 tAVAV tAVQV tAXQX A0-A16 DQ0-DQ15 VALID DATA VALID DATA VALID PROCED |
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