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M36DR232 数据表(PDF) 37 Page - STMicroelectronics

部件名 M36DR232
功能描述  32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 2 Mbit 128K x16 SRAM, Multiple Memory Product
PDF  46 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M36DR232 数据表(HTML) 37 Page - STMicroelectronics

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M36D232A, M36DR232B
Table 32. SRAM Write AC Characteristics
(TA = –40 to 85°C; VDDS = 1.65V to 2.2V)
Note: 1. tAS is measured from the address valid to the beginning of write.
2. tWR is measured from the end or write to the address change. tWR appliedincaseawrite ends as E1S or WS going high.
3. tCW is measured from E1S going low end of write.
4. A Write occurs during the overlap (tWP)of low E1S and low WS. A write begins when E1S goes low and WS goes low with asserting
UBS or LBS for single byte operation or simultaneously asserting UBS and LBS for double byte operation. A write ends at the ear-
liest transition when E1S goes high and WS goes high. The tWP is measured from the beginning of write to the end of write.
Symbol
Alt
Parameter
SRAM
Unit
Min
Max
tAVAV
tWC
Write Cycle Time
70
ns
tAVE1L
tAS
(1)
Address Valid to Chip Enable 1 Low
0
ns
tAVE2H
tAS
(1)
Address Valid to Chip Enable 2 High
0
ns
tAVWH
tAW
Address Valid to Write Enable High
60
ns
tAVWL
tAS
(1)
Address Valid to Write Enable Low
0
ns
tBLWH
tBW
UBS, LBS Valid to End of Write
60
ns
tDVE1H
tDW
Input Valid to Chip Enable 1 High
40
ns
tDVE2L
tDW
Input Valid to Chip Enable 2 Low
40
ns
tDVWH
tDW
Input Valid to Write Enable High
40
ns
tE1HAX
tWR
(2)
Chip Enable 1 High to Address Transition
0
ns
tE1LWH,
tE2HWH
tCW
(3)
Chip Select to End of Write
60
ns
tE2LAX
tWR
(2)
Chip Enable 2 Low to Address Transition
0
ns
tGHQZ
tGHZ
Output Enable Higt to Output Hi-Z
0
25
ns
tWHAX
tWR
(2)
Write Enable High to Address Transition
0
ns
tWHDX
tDH
Write Enable High to Input Transition
0
ns
tWHQX
tOW
Write Enable High to Output Transition
5
ns
tWLQZ
tWHZ
Write Enable Low to Output Hi-Z
0
25
ns
tWLWH
tWP
(4)
Write Enable Pulse Width
50
ns



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