M39832 datasheet(8/36 Pages) STMICROELECTRONICS

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Operation

VIL

VIH

VIL

VIH

Read in Flash Array

VIH

VIL

VIH

Read in EEPROM Array

VIL

VIH

VIL

Write in Flash Array

VIH

VIL

VIH

VIL

Write in EEPROM Array

VIL

VIH

Output Disable, DQn = Hi-Z

VIH

VIL

VIH

Output Disable, DQn = Hi-Z

VIH

Standby, DQn = Hi-Z

Note: X = VIL or VIH.

Table 4. Basic Operations

Write Enable (W). Addresses are latched on the

falling edge of W, and Data Inputs are latched on

the rising edge of W.

EEPROM Ready/Busy (ERB) . The EEPROM

Ready/Busy pin outputs the status of the device

when the EEPROM memory array is under the

write condition

–ERB = ’0’: internal writing is in process,

–ERB = ’1’: no internal writing in in process.

This status pin can be used when reading (or

fetching opcodes) in the Flash memory array.

The EEPROM Ready/Busy output uses an open

drain transistor, allowing therefore the use of the

M39832 in multi-memory applications with all

Ready/Busy outputs connected to a single

Ready/Busy line (OR-wired with an external pull-up

resistor).

Flash Ready/Busy (FRB). Flash Ready/Busy is an

open-drain output and gives the internal state of

Flash array. When FRB is Low, the Flash array is

Busy with a Program or Erase operation and it will

not accept any additional program or erase instruc-

tions except the Erase Suspend instruction. When

FRB is High, the Flash array is ready for any Read,

Program or Erase operation. The FRB will also be

High when the Flash array is put in Erase Suspend

or Standby modes.

Reset/Block Temporary Unprotect Input (RP).

The RP Input provides hardware reset of the Flash

array and temporary unprotection of the protected

Flash block(s). Reset of the Flash array

acheived by pulling RP to VIL for at least tPLPX.

When the reset pulse is given while the Flash array

is in Read or Standby modes, it will be available for

new operations in tPHEL after the rising edge of RP.

If the Flash array is in Erase, Erase Suspend or

Program modes the reset will take tPLYH during

which the FRB signal will be held at VIL. The end

of the Flash array reset will be indicated by the

rising edge of FRB. A hardware reset during an

Erase or Program operation will corrupt the data

being programmed or the block(s) being erased.

See Table 14 and Figure 9. Temporary block unpro-

tection is made by holding RP at VID. In this condi-

tio n, pr ev iously protected bloc ks can be

programmed or erased. The transition of RP from

VIH to VID must be slower than tPHPHH. See Table

15 and Figure 9. When RP is returned from VID to

VIH all blocks temporarily unprotected will be again

protected.

OPERATIONS

An operation is defined as the basic decoding of

the logic level applied to the control input pins (EF,

EE, G, W) and the specified voltages applied on

the relevant address pins. These operations are

detailed in Table 3.

Read. Both Chip Enable and Output Enable (that

is EF and G or EE and G) must be low in order to

read the output of the memory.

Read operations are used to output the contents

from the Flash or EEPROM array, the Manufacturer

identifier, the Flash Block protection Status, the

Flash Identifier, the EEPROM identifier or the OTP

row content.

Notes:

– The Chip Enable input mainly provides power

control and should be used for device selection.

The Output Enable input should be used to gate

data onto the output in combination with active

EF or EE input signals.

– The data read depends on the previous instruc-

tion entered into the memory.

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