M39832 datasheet(2/36 Pages) STMICROELECTRONICS

2 / 36 page

Warning: NC = Not Connected.

VSS

DQ8

DQ1

DQ14

A10

DQ12

A15

DQ10

DQ6

VCC

DQ9

DQ2

DQ3

DQ11

DQ4

A18

FRB

A17

AI00845

M39832

DQ13

ERB

DQ5

DQ0

A16

BYTE

VSS

DQ15A–1

DQ7

A13

A14

A12

A11

Figure 2. TSOP Pin Connections

A0-A18

Address Inputs

DQ0-DQ7

Data Input/Outputs, Commands Input

DQ8-DQ14

Data Input/Outputs

DQ15A–1

Data Input/Outputs or Address Input

EEPROM Array Enable

Flash Array Enable

Output Enable

Write Enable

Reset/Block Temporary Unprotect

ERB

EEPROM Ready/Busy Output

FRB

Flash Ready/Busy Output

BYTE

Flash Array Byte/Word Organization

VCC

Supply Voltage

VSS

Ground

Table 1. Signal Names

DESCRIPTION (cont’d)

The M39832 Flash Memory array can be config-

ured as 1Mb x8 or 512Kb x16 with the BYTE input

pin. The M39832-T and M39832-B feature asymet-

rically blocked architecture providing system mem-

ory integration. Both M39832-B and M39832-T

devices have a Flash array of 19 blocks, one Boot

Block of 16 KBytes or 8 KWords, two Parameter

Blocks of 8 KBytes or 4 KWords, one Main Block

of 32 KBytes or 16 KWords and fifteen Main Blocks

of 64 KBytes or 32 KWords. The M39832-T has the

Boot Block at the top of the memory address space

and the M39832-B locates the Boot Block starting

at the bottom. The memory maps are showed in

Figures 3A and 3B. Each block can be erased

separately,any combination of blocks can be speci-

fied for multi-block erase or the entire chip may be

erased. The Erase operations are managed auto-

matically. The block erase operation can be sus-

pended in order to read from or program to any

block not being ersased, and then resumed. Block

protection provides additional data security. Each

block can be separately protected or unprotected

against Program or Erase on programming equip-

ment. All previously protected blocks can be tem-

porarily unprotected in the application. The Flash

memory array is functionally compatible with the

M29W800 Single Voltage Flash Memory device.

During a Program or Erase cycle in the Flash array

or during a Write in the EEPROM array, status bits

available on certain DQn pins provide information

on the M39832 internal logic.

PIN DESCRIPTION

Byte/Word Organization Select (BYTE). The

BYTE input selects the output configuration for the

Flash array: Byte-wide (x8) mode or Word-wide

(x16) mode. The EEPROM array and the 64 Bytes

OTP Row are always accessed Byte-wide (x8).

When BYTE is High, the Word-wide mode is se-

lected for the Flash array (x16) and the data are

read and programmed on DQ0-DQ15. The Flash

array is accessed with A0-A18 Adrress lines. In this

mode, data in the EEPROM array (x8) are read and

programmed on DQ0-DQ7 and the array is ac-

cessed with A0-A14. The 64 bytes OTP are read

and programmed on DQ0-DQ7 and are accessed

with A0-A5 and A6 = 0.

When BYTE is Low, the Byte-wide mode is selected

for the Flash array (x8) and the data are read and

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M39832

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