AI00844

19

A0-A18

EE

DQ0-DQ14

VCC

M39832

G

EF

VSS

15

W

ERB

RP

FRB

DQ15A–1

BYTE

Figure 1. Logic Diagram

M39832

Single Chip 8 Mbit (1Mb x8 or 512Kb x16) Flash and

256 Kbit Parallel EEPROM Memory

PRELIMINARY DATA

2.7V to 3.6V SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPARATIONS

FLASH ARRAY

– Boot block (Top or Bottom location)

– Parameter and Main blocks

– Selectable x8/x16 Data Bus (BYTE pin).

EEPROM ARRAY

– x8 Data Bus only.

120ns ACCESS TIME

(Flash and EEPROM array)

WRITE, PROGRAM and ERASE STATUS BITS

CONCURRENT MODE (Read Flash while

writing to EEPROM)

100,000 ERASE/WRITE CYCLES

10 YEARS DATA RETENTION

LOW POWER CONSUMPTION

– Stand-by mode: 100

µA

– Automatic Stand-by mode

64 bytes ONE TIME PROGRAMMABLE

MEMORY (x8 Data Bus only)

STANDARD EPROM/OTP MEMORY

PACKAGE

EXTENDED TEMPERATURE RANGES

DESCRIPTION

The M39832 is a memory device combining Flash

and EEPROM into a single chip and using single

supply voltage. The memory is mapped in two

arrays: 8 Mbit of Flash memory and 256 Kbit of

EEPROM memory. Each space is independant for

writing, in concurrent mode the Flash Memory can

be read while the EEPROM is being written.

An additional 64 bytes of EPROM are One Time

Programmable.

The M39832 EEPROM memory array is organized

in byte only (regardless on the BYTE pin). It may

be written by byte or by page of 64 bytes and the

integrity of the data can be secured with the help

of the Software Data Protection (SDP).

TSOP48 (NE)

12 x 20 mm

February 1999

1/36

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.