programmed on DQ0-DQ7. In this mode, DQ8-

DQ14 are at high impedance and DQ15A–1 is the

LSB address bit, making the Flash array to be

accessed with A–1-A18 Adress lines. In this mode,

data in the EEPROM array (x8) are read and

programmed on DQ0-DQ7 and the array is ac-

cessed with A–1-A13. The 64 bytes OTP are read

and programmed on DQ0-DQ7 and are accessed

with A-1 - A4 and A6 = 0.

Address Inputs (A0-A18). The address inputs for

the memory array are latched during a write opera-

tion on the falling edge at Chip Enable (EE or EF)

or Write Enable W. In Word-wide organisation the

address lines are A0-A18, in Byte-wide organisa-

tion DQ15A–1 acts as an additional LSB address

Electronic Signature Manufacturer or Device Code,

Block Protection Status or a Write Block Protection

or Block Unprotection is enabled depending on the

combination of levels on A0, A1, A6, A12 and A15.

Data Input/Output (DQ0-DQ7).

The s e In-

puts/Outputs are used in the Byte-wide and Word-

wide organisations. The input is data to be

programmed in the memory array or a command

to be written. Both are latched on the rising edge

of Chip Enable (EE or EF) or Write Enable W. The

output is data from the Memory Array, the Elec-

tronic Signature Manufacturer or Device codes, the

Block Protection Status or the Status register Data

Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the

Error bit DQ5 or the Erase Timer bit DQ3. Outputs

are valid when Chip Enable (EE or EF) and Output

Enable G are active. The output is high impedance

when the chip is deselected or the outputs are

disabled and when RP is at a Low level.

Data Input/Outputs (DQ8-DQ14 and DQ15A–1).

These Inputs/Outputs are additionally used in the

Word-wide organisation. When BYTE is High DQ8-

DQ14 and DQ15A–1 act as the MSB of the Data

Input or Output, functioning as described for DQ0-

DQ7 above, and DQ8 - DQ15 are ’don’t care’ for

command inputs or status outputs. When BYTE is

Low, DQ8-DQ14 are high impedance, DQ15A–1 is

the Address A–1 input.

Memory Array Enable (EE and EF). The Memory

Array Enable (EE or EF) activates the memory

control logic, input buffers, decoders and sense

amplifiers. When the EE input is driven high, the

EEPROM memory array is not selected; when the

EF input is driven high, the Flash memory array is

not selected. Attempts to access both EEPROM

and Flash arrays (EE low and EF low) are forbid-

den. Switching between the two memory array

enables (EE and EF) must not be made on the

be inserted.

The M39832 is in standby when both EF and EE

are High (when no internal Erase or programming

is running). The power consumption is reduced to

the standby level and the outputs are in the high

impedance state, independent of the Output En-

able G or Write Enable W inputs.

After 150ns of inactivity and when the addresses

are driven at CMOS levels, the chip automatically

enters a pseudo standby mode where consumption

is reduced to the CMOS standby value, while the

outputs continue to drive the bus.

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read

operation. The data outputs are in the high imped-

ance state when the Output Enable G is High.

During Block Protect and Block Unprotect opera-

+ 0.5V) (for Flash memory array only).

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

–40 to 85

°C

Temperature Under Bias

–50 to 125

°C

Storage Temperature

–65 to 150

°C

(2)

Input or Output Voltages

–0.6 to 5

V

Supply Voltage

–0.6 to 5

V

(2)

A9, G, EF Voltage

–0.6 to 13.5

V

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

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M39832