M39832 datasheet(21/36 Pages) STMICROELECTRONICS

21 / 36 page

Erase Suspend (ES) Instruction. The Block

Erase operation may be suspended by this instruc-

tion which consists of writing the command B0h

without any specific address. No Coded cycles are

required. It permits reading of data from another

block and programming in another block while an

erase operation is in progress. Erase suspend is

accepted only during the Block Erase instruction

execution. Writing this command during Erase

timeout will, in addition to suspending the erase,

terminate the timeout. The Toggle bit DQ6 stops

toggling when erase is suspended. The Toggle bits

will stop toggling between 0.1ms and 15ms after

the Erase Suspend (ES) command has been writ-

ten. The device will then automatically be set to

Read Memory Array mode. When erase is sus-

pended, a Read from blocks being erased will

output DQ2 toggling and DQ6 at ’1’. A Read from

a block not being erased returns valid data. During

suspension the memory will respond only to the

Erase Resume ER and the Program PG instruc-

tions.

A Program operation can be initiated during erase

suspend in one of the blocks not being erased. It

will result in both DQ2 and DQ6 toggling when the

data is being programmed. A Read/Reset com-

mand will definitively abort erasure and result in

invalid data in the blocks being erased.

Erase Resume (ER) Instruction. If an Erase Sus-

pend instruction was previously executed, the

erase operation may be resumed by giving the

command 30h, at any address, and without any

Coded cycles.

FLASH ARRAY SPECIFIC FEATURES

Block Protection (See Figure 8). Each block can

be separately protected against Program or Erase

on programming equipment. Block protection pro-

vides additional data security, as it disables all

program or erase operations. This mode is acti-

vated when both A9 and G are raised to VID and an

address in the block is applied on A12-A18. Block

protection is initiated on the edge of W falling to VIL.

Then after a delay of 100ms, the edge of W rising

to VIH ends the protection operations. Block protec-

tion verify is achieved by bringing G, EF, A0 and A6

to VIL and A1 to VIH, while W is at VIH and A9 at VID.

AI00939

VCC / 2

VCC

Figure 10. AC Testing Input Output Waveform

AI00854

VCC

CL = 30pF

CL includes JIG capacitance

VOUT = 1.5V when the DEVICE

UNDER TEST is in the

Hi-Z output state.

1N914

DEVICE

UNDER

TEST

1N914

IOH

IOL

Figure 11. Output AC Testing Load Circuit

Symbol

Parameter

Test Condition

Min

Max

Unit

CIN

Input Capacitance

VIN = 0V

COUT

Output Capacitance

VOUT = 0V

Note: 1. Sampled only, not 100% tested.

Table 11. Capacitance (1) (TA = 25

°C, f = 1 MHz )

Input Rise and Fall Times

≤ 10ns

Input Pulse Voltages

0.V to VCC

Input and Output Timing Ref.

Voltages

VCC / 2

Table 10. AC Measurement Conditions

21/36

M39832

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