ST7LITE1XB datasheet(67/157 Pages) STMICROELECTRONICS

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ST7LITE1xB

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DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)

11.2.3.6 One Pulse Mode

One Pulse Mode can be used to control PWM2/3

signal with an external LTIC pin. This mode is

available only in dual timer mode i.e. only for

CNTR2, when the OP_EN bit in PWM3CSR regis-

ter is set.

One Pulse Mode is activated by the external LTIC

input. The active edge of the LTIC pin is selected

by the OPEDGE bit in the PWM3CSR register.

After getting the active edge of the LTIC pin,

CNTR2 is reset (000h) and PWM3 is set to high.

CNTR2 starts counting from 000h, when it reaches

the active DCR3 value then the PWM3 output

goes low. Till this time, any further transitions on

the LTIC signal will have no effect. If there are

LTIC transitions after CNTR2 reaches the DCR3

value, CNTR2 is reset again and the PWM3 output

goes high.

If there is no LTIC active edge then CNTR2 will

count till it reaches the ATR2 value, and then it will

be reset again and the PWM3 output is set to high.

The counter again starts counting from 000h,

when it reaches the active DCR3 value the PWM3

output goes low, the counter counts till it reaches

the ATR2 value, it resets and the PWM3 output is

set to high and it goes on the same way.

The same operation applies for the PWM2 output,

but in this case the comparison is done on the

DCR2 value.

The OP_EN and OPEDGE bits take effect on the

fly and are not synchronized with the CNTR2 over-

flow.

The OP2/3 bits can be used to inverse the polarity

of the PWM2/3 outputs in one-pulse mode. The

update of these bits (OP2/3) is synchronized with

the CNTR2 overflow, they will be updated if the

TRAN2 bit is set.

Notes:

1. The time taken from activation of LTIC input and

CNTR2 reset is between 1 and 2 tcpu cycles, i.e.

125 ns to 250 ns (with 8 MHz fcpu)

2. The Lite Timer input capture interrupt must be

disabled while 12-bit ARTimer is in One Pulse

Mode. This is to avoid spurious interrupts.

3. The priority of various events affecting PWM3 is

as follows:

– Break (Highest priority)

– One-pulse mode with active LTIC edge

– Forced overflow (by FORCE2 bit)

– One-pulse mode without active LTIC edge

– Normal PWM operation. (Lowest priority)

4. It is possible to synchronize the update of

DCR2/3 registers and OP2/3 bits with the CNTR2

reset. This is managed by the overflow interrupt

which is generated if CNTR2 is reset either due to

an ATR match or an active pulse on the LTIC pin.

5. Updating the DCR2/3 registers and OP2/3 bits

in one-pulse mode is done dynamically by soft-

ware using force update (FORCE2 bit in the

ATCSR2 register).

6. DCR3 update in this mode is not synchronized

with any event. Consequently the next PWM3 cy-

cle just after the change may be longer than ex-

pected (refer to Figure 49).

7. In One Pulse Mode the ATR2 value must be

greater than the DCR2/3 value for the PWM2/3

outputs. (contrary to normal PWM mode)

8. If there is an active edge on the LTIC pin after

the CNTR2 has reset due to an ATR2 match, then

the timer gets reset again. The duty cycle may be

modified depending on whether the new DCR val-

ue is less than or more than the previous value.

9. The TRAN2 bit must be set simultaneously with

the FORCE2 bit in the same instruction after a

write to the DCR register.

10. The ATR2 value should be changed after an

overflow in one pulse mode to avoid an irregular

PWM cycle.

11. When exiting from one pulse mode, the

OP_EN bit in the PWM3CSR register must be re-

set first and then the ENCNTR2 bit (if CNTR2 is to

be stopped).

How to Enter One Pulse Mode:

1. Load the ATR2H/ATR2L registers with required

value.

2. Load the DCR3H/DCR3L registers for PWM3

output. The ATR2 value must be greater than

DCR3.

3. Set the OP3 bit in the PWM3CSR register if po-

larity change is required.

4. Start the CNTR2 counter by setting the

ENCNTR2 bit in the ATCSR2 register.

5. Set TRAN2 bit in ATCSR2 to enable transfer.

6. Wait for an overflow event by polling the OVF2

flag in the ATCSR2 register.

7. Select the counter clock using the CK[1:0] bits in

the ATCSR register.

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