ST7LITE1XB datasheet(35/157 Pages) STMICROELECTRONICS

35 / 157 page

ST7LITE1xB

35/157

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.4 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read/Write

Reset Value: 0110 0xx0 (6xh)

Bit 7 = LOCK32 PLL 32Mhz Locked Flag

This bit is set and cleared by hardware. It is set au-

tomatically when the PLL 32Mhz reaches its oper-

ating frequency

0: PLL32 not locked

1: PLL32 locked

Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad-

justment bits

These bits, as well as CR[9:2] bits in the RCCR

adjust the RC oscillator frequency and to obtain an

accuracy of 1%. Refer to section 7.3 on page 25.

Bit 4 = WDGRF Watchdog Reset flag

This bit indicates that the last Reset was generat-

ed by the Watchdog peripheral. It is set by hard-

ware (watchdog reset) and cleared by software

(writing zero) or an LVD Reset (to ensure a stable

cleared state of the WDGRF flag when CPU

starts).

Combined with the LVDRF flag information, the

flag description is given by the following table.

Bit 3 = LOCKED PLL Locked Flag

This bit is set and cleared by hardware. It is set au-

tomatically when the PLL reaches its operating fre-

quency.

0: PLL not locked

1: PLL locked

Bit 2 = LVDRF LVD reset flag

This bit indicates that the last Reset was generat-

ed by the LVD block. It is set by hardware (LVD re-

set) and cleared by software (by reading). When

the LVD is disabled by OPTION BYTE, the LVDRF

bit value is undefined.

Bit 1 = AVDF Voltage Detector Flag

This read-only bit is set and cleared by hardware.

If the AVDIE bit is set, an interrupt request is gen-

erated when the AVDF bit is set. Refer to Figure

20 and to Section 7.6.2.1 for additional details.

0: VDD over AVD threshold

1: VDD under AVD threshold

Bit 0 = AVDIE Voltage Detector Interrupt Enable

This bit is set and cleared by software. It enables

an interrupt to be generated when the AVDF flag is

set. The pending interrupt information is automati-

cally cleared when software enters the AVD inter-

rupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

Application notes

The LVDRF flag is not cleared when another RE-

SET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the origi-

nal failure.

In this case, a watchdog reset can be detected by

software while an external reset can not.

PLL TEST REGISTER (PLLTST)

Read/Write

Reset Value: 0000 0000(00h)

Bit 7 : PLLdiv2 PLL clock divide by 2

This bit is read or write by software and cleared by

hardware after reset. This bit will divide the PLL

output clock by 2.

0 : PLL output clock

1 : Divide by 2 of PLL output clock

Refer “Clock Management Block Diagram” on

page 26

Note : Write of this bit will be effective after 2 Tcpu

cycles (if system clock is 8mhz) else 1 cycle (if

system clock is 4mhz) i.e. effective time is 250ns.

Bit 6:0 : Reserved , Must always be cleared

LOCK

CR1 CR0

WDG

LOCKED LVDRF AVDF AVDIE

RESET Sources

LVDRF

WDGRF

External RESET pin

Watchdog

LVD

PLLdiv2

ST7LITE1XB 数据表(PDF) 35 Page - STMicroelectronics

ST7LITE1XB 数据表(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载