 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ST7LITE1XB 数据表(PDF) 68 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST7LITE1XB 数据表(HTML) 68 Page - STMicroelectronics |
|
|
68 / 157 page  ST7LITE1xB 68/157 DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) 8. Set the OP_EN bit in the PWM3CSR register to enable one-pulse mode. 9. Enable the PWM3 output by setting the OE3 bit in the PWMCR register. The "Wait for Overflow event" in step 6 can be re- placed by forced update (writing the FORCE2 bit). Follow the same procedure for PWM2 with the bits corresponding to PWM2. Note: When break is applied in one-pulse mode, the CNTR2, DCR2/3 & ATR2 registers are reset. Consequently, these registers have to be initial- ized again when break is removed. Figure 47. Block Diagram of One Pulse Mode Figure 48. One Pulse Mode and PWM Timing Diagram LTIC pin Edge Selection OPEDGE PWM3CSR Register OP_EN 12-bit AutoReload Register 2 12-bit Upcounter 2 12-bit Active DCR2/3 Generation PWM OP2/3 PWM2/3 OVF ATR2 CNTR2 LTIC PWM2/3 000 DCR2/3 000 DCR2/3 ATR2 000 OVF ATR2 DCR2/3 OVF ATR2 DCR2/3 CNTR2 LTIC PWM2/3 fcounter2 fcounter2 Note 1: When OP_EN=0, LTIC edges are not taken into account as the timer runs in PWM mode. 1 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
