1/52

PRELIMINARY DATA

August 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M58MR032C

M58MR032D

32 Mbit (2Mb x16, Mux I/O, Dual Bank, Burst)

1.8V Supply Flash Memory

s

SUPPLY VOLTAGE

Erase and Read

s

MULTIPLEXED ADDRESS/DATA

s

SYNCHRONOUS / ASYNCHRONOUS READ

– Burst mode Read: 40MHz

– Page mode Read (4 Words Page)

– Random Access: 100ns

s

PROGRAMMING TIME

– 10µs by Word typical

– Two or four words programming option

s

MEMORY BLOCKS

– Dual Bank Memory Array: 8/24 Mbit

– Parameter Blocks (Top or Bottom location)

s

DUAL OPERATIONS

– Read within one Bank while Program or

Erase within the other

– No delay between Read and Write operations

s

PROTECTION/SECURITY

– All Blocks protected at Power-up

– Any combination of Blocks can be protected

– 64 bit unique device identifier

– 64 bit user programmable OTP cells

– One parameter block permanently lockable

s

COMMON FLASH INTERFACE (CFI)

s

100,000 PROGRAM/ERASE CYCLES per

BLOCK

s

ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Device Code, M58MR032C: 88DAh

– Bottom Device Code, M58MR032D: 88DBh

FBGA

TFBGA48 (ZC)

10 x 4 ball array

Figure 1. Logic Diagram

AI90019

5

A16-A20

W

ADQ0-ADQ15

VDD

M58MR032C

M58MR032D

E

VSS

16

G

RP

WP

VDDQ VPP

L

K

WAIT

BINV