M58MR032C datasheet(18/52 Pages) STMICROELECTRONICS

18 / 52 page

M58MR032C, M58MR032D

18/52

BLOCK PROTECTION

The M58MR032C/M58MR032D provide a flexible

protection of all the memory providing the protec-

tion, un-protection and locking of any blocks. All

blocks are protected at power-up. Each block of

the array has two levels of protection against pro-

gramming or erasing operation. The first level is

set by the Block Protect instruction; a protected

block cannot be programmed or erased until a

Block Unprotect instruction is given for that block.

A second level of protection is set by the Block

Lock instruction, and requires the use of the WP

pin, according to the following scheme:

– when WP is at VIH, the Lock status is overridden

and all blocks can be protected or unprotected;

– when WP is at VIL, Lock status is enabled; the

locked blocks are protected, regardless of their

previous protect state, and protection status

cannot be changed. Blocks that are not locked

can still change their protection status;

– the lock status is cleared for all blocks at power

up.

The protection and lock status can be monitored

for each block using the Read Electronic Signature

(RSIG) instruction. Protected blocks will output a

'1' on DQ0 and locked blocks will output a '1' in

DQ1 (see Table 13).

PROTECTION REGISTER PROGRAM (PRP)

and LOCK PROTECTION REGISTER

PROGRAM (LPRP)

The M58MR032C/M58MR032D features a 128-bit

protection register and a security Block in order to

increase the protection of a system design. The

Protection Register is divided in two 64-bit seg-

ments. The first segment (81h to 84h) is a unique

device number, while the second one (85h to 88h)

can be programmed by the user. When shipped

the user programmable segment is read at '1'. It

can be only programmed at '0'.

The user programmable segment can be protect-

ed writing the bit 1 of the Protection Lock register

(80h). The bit 1 protects also the bit 2 of the Pro-

tection Lock Register.

The M58MR032C/M58MR032D feature a security

Block. The security Block is located at 1FF000-

1FFFFF (M58MR032C) or at 000000-000FFF

(M58MR032D) of the device. This block can be

permanently protected by the user programming

the bit 2 of the Protection Lock Register (see Fig-

ure 5).

The protection Register and the Protection Lock

structions. A subsequent read in the address start-

ing from 80h to 88h, the user will retrieve

respectively the Protection Lock register, the

unique device number segment and the OTP user

programmable register segment (see Table 23).

WRITE READ CONFIGURATION REGISTER

(CR).

This instruction uses two Coded Cycles, the first

write cycle is the write Read Configuration Regis-

ter set-up 60h, the second write cycle is write

Read Configuration Register confirm 03h both to

Read Configuration Register address (see Table

11).

This instruction writes the contents of address bits

ADQ15-ADQ0 to bits CR15-CR0 of the Read Con-

figuration Register (A20-A16 are don't care). At

Power-up the Read Configuration Register is set

to asynchronous Read mode, Power-down dis-

abled and bus invert (power save function) dis-

abled. A description of the effects of each

configuration bit is given in Table 14.

Read mode (CR15). The

device

supports

asynchronous page mode and a synchronous

burst mode. In asynchronous page mode, the de-

fault at power-up, data is internally read and stored

in a buffer of 4 words selected by ADQ0 and ADQ1

address inputs. In synchronous burst mode, the

device latches the starting address and then out-

puts a sequence of data that depends on the Read

Configuration Register settings (see Figures 10,

11 and 12).

Synchronous burst mode is supported in both pa-

rameter and main blocks; it is also possible to per-

form burst mode read across the banks.

Bus Invert configuration (CR14). This

bit is used to enable the BINV pin functionality.

BINV functionality depends upon configuration

bits CR14 and CR15 (see Table 14 for configura-

tion bits definition) as shown in Table 15. As output

pin BINV is active only when enabled (CR14 = 1)

in Read Array burst mode (CR15 = 0). As input pin

BINV is active only when enabled (CR14 = 1).

BINV is ignored when ADQ0-ADQ15 lines are

used as address inputs (addresses must not be in-

verted).

X-Latency (CR13-CR11). These

configuration

bits define the number of clock cycles elapsing

from L going low to valid data available in burst

mode (see Figure 6). The correspondence be-

tween X-Latency settings and the maximum sus-

tainable frequency must be calculated taking into

account some system parameters.

Two conditions must be satisfied:

–(n + 2) tK ≥ tACC + tQVK_CPU + tAVK_CPU

–tK > tKQV + tQVK_CPU

where "n" is the chosen X-Latency configuration

code, tK is the clock period, tAVK_CPU is the ad-

dress setup time guaranteed by the system CPU,

and tQVK_CPU is the data setup time required by

the system CPU.

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