M7010R datasheet(62/67 Pages) STMICROELECTRONICS

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M7010R

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Table 36. Right-Shift of SRAM Signals for TLSZ

Values

Table 37. Right-Shift of SRAM Signals for

HLAT Values

JTAG (1149.1) TESTING

The M7010R supports the Test Access Port (TAP)

and Boundary Scan Architecture as specified in

the IEEE JTAG standard 1149.1. The pin interface

to the chip consists of five signals with the stan-

dard definitions: TCK, TMS, TDI, TDO, and

TRST_L. Table 38, page 62 describes the opera-

tions that the test access port controller supports.

Table 39 shows the TAP Device ID Register.

Note: To disable JTAG functionality, connect the

TCK, TMS, and TDI pins to VDDQ through a pull-

up, and the TRST_L to ground through a pull-

down.

Table 38. Test Access Port Controller Instructions

Table 39. TAP Device ID Register

TLSZ

Number of CLK Cycles

HLAT

Number of CLK Cycles

000

001

010

011

100

101

110

111

Instruction

Type

Description

SAMPLE/PRELOAD

Mandatory

Sample/Preload. Loads the values of signals going to and from IO

pins into the boundary scan shift register to provide a snapshot of the

normal functional operation.

EXTEST

Mandatory

External Test. Uses boundary scan values shifted in from TAP to test

connectivity external to the device.

INTEST

Optional

Internal Test. Allows slow-speed, functional testing of the device

using the boundary scan register to provide the I/O values.

Field

Range

Initial Value

Description

Revision

[31:28]

0001

Revision Number. This is the current device revision number.

Numbers start from one and increment by one for each revision of the

device.

Part #

[27:12]

0000 0000 0000 0001 This is the part number for this device.

MFID

[11:1]

000_1101_1100

Manufacturer ID. This field is the same as the manufacturer ID used

in the TAP controller.

LSB

[0:0]

Least Significant Bit

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