M7010R datasheet(52/67 Pages) STMICROELECTRONICS

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M7010R

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DEPTH-CASCADING

The Search Engine application can depth-cas-

cade the device to various table sizes in 68-bit,

136-bit, and 272-bit configurations by program-

ming the table size (TLSZ) field of the Command

arbitration to decide which device drives the

SRAM Bus. The latency of the searches increases

as the table size increases while the search rate

remains constant.

Depth-Cascading Up to Eight Devices (One

Block)

Figure 38, page 53 shows how up to eight devices

can cascade to form a 128K x68-bit, 64K x136-bit,

or 32K x272-bit table. It also shows the intercon-

nection between the devices for depth-cascading.

The host ASIC must program the table size (TLSZ)

field to '01.' Each Search Engine asserts the

LHO[1] and LHO[0] signals to inform downstream

devices in the cascade of its results. The LHI[6:0]

signals for any device are connected to the LHO

signals of the upstream device. A single device

alone drives the SRAM bus in any given cycle.

Depth-Cascading Up to 31 Devices (4 Blocks)

Figure 39, page 54 shows how to cascade up to

four blocks. Each block contains up to eight

M7010Rs (except the last block, which contains 7

devices), to form a 496K x68, 248K x136, or 124K

x272 table. Note the interconnection between

blocks for depth-cascading. The host ASIC must

program the table size (TLSZ) field to 10 for cas-

cading 8 to 31 devices (in up to four blocks). For

each search, a block asserts BHO[2], BHO[1], and

BHO[0].The BHO[2:0] signals for a block are only

taken from the last device in the block. See Figure

41, page 56 for the arbitration cycle between

blocks to determine which device drives the SRAM

Bus.

The device is configured to be the last in the

depth-cascaded table by setting LDEV to 1 in the

Command Register. The device with LDEV set to

1 drives the SSF and SSV signals in cycles when

all upstream devices do not drive these signals.

The M7010R with its LDEV Bit set drives SSF and

SSV during a search with a miss or with non-

search commands. See the LDEV Bit definition in

Table 10, page 20.

Depth-Cascading to Generate a “FULL” State

for a Block

Bit[0] of each of the 68-bit entries is designated as

a special bit (1 = FULL; 0 = Empty). For each

LEARN or PIO WRITE to the data array, each de-

vice asserts FULO[1] and FULO[0] if it does not

have any empty locations (see Figure 40, page

55). Each device combines the FULO signals from

the devices above it with its own full status to gen-

erate a FULL signal, which will then give a “full”

status of the table up to the device asserting the

FULL signal. Figure 40, page 55 shows the hard-

ware connection diagram for generating the FULL

signal that goes back to the ASIC. In a depth-cas-

caded block of up to eight devices, the FULL sig-

nal from the last device should be fed back to the

ASIC controller to indicate the fullness of the table.

The FULL signal of the other devices should be left

open.

Note: The LEARN Instruction is supported for up

to eight devices, whereas FULL cascading is al-

lowed for one block in tables containing more than

eight devices. In tables for which a LEARN Instruc-

tion will not be used, the Bit[0] of each 68-bit entry

shouldalways beset to '1.'

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