M7010R datasheet(27/67 Pages) STMICROELECTRONICS

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M7010R

COMMAND CODES AND PARAMETERS

A master device, such as an ASIC controller, is-

sues commands to the M7010R using the CMDV

signal and the CMD Bus. The following subsec-

tions describe the functions of the commands.

Command Codes

The M7010R implements four basic commands

shown in Table 16. The Command code must be

presented to CMD[1:0] while keeping the com-

mand valid (CMDV) signal high for two CLK2X cy-

cles. These two CLK2X cycles are designated as

“Cycle A” and “Cycle B.” The CMD[8:2] field pass-

es the parameters of the command in CLK2X Cy-

cles A and B. The controller ASIC must align the

instructions with the CLK2X signal.

Commands and Command Parameters

Table 17 lists the CMD bus fields that contain the

M7010R command parameters as well as their re-

spective cycles.

Table 16. Command Codes

Table 17. Command Parameters

Note: The SRAM Address Bit SADR [19] in the command bit C6 will not be passed to the SRAM (see Table 28).

1. The 272-bit configuration does not support the LEARN Instruction.

CMD Code

Command

Description

READ

Reads one of the following: data array, mask array, device registers, or external

SRAM.

WRITE

Writes one of the following: data array, mask array, device registers, or external

SRAM.

Searches the data array for a desired pattern using the specified register from the

global mask register array and local mask associated with each data cell.

LEARN

The device has internal storage for up to 16 comparands that it can learn. The

device controller can insert these entries at the next free address (as specified by

the NFA register) using the LEARN Instruction.

Cmd

Cyc

READ

SADR[21]

SADR[20]

SADR[19]

0 = Single

1 = Burst

0 = Single

1 = Burst

WRITE

SADR[21]

SADR[20]

SADR[19]

GMR Index[2:0]

0 = Single

1 = Burst

GMR Index[2:0]

0 = Single

1 = Burst

SADR[21]

SADR[20]

SADR[19]

GMR Index[2:0]

68-bit or 136-bit: 0

272-bit:

1 in 1st Cycle

0 in 2nd Cycle

Successful SEARCH Register Index[2:0]

Comparand Register Index

LEARN

(1)

SADR[21]

SADR[20]

SADR[19]

Comparand Register Index

Mode

0: 68-bit

1: 136-bit

Comparand Register Index

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