M7010R datasheet(38/67 Pages) STMICROELECTRONICS

38 / 67 page

M7010R

38/67

136-bit Configuration

Figure 28, page 39 shows the timing diagram for

the SEARCH operation in the 136-bit table (CFG =

01010101) consisting of a single device for one set

of parameters: TLSZ = 00, HLAT = 001, LRAM =

1, and LDEV = 1. The hardware diagram for the

search subsystem is shown in Figure 27.

The following is the operation sequence for a sin-

gle, 136-bit SEARCH command.

– Cycle A: The host ASIC drives the CMDV high

and applies the SEARCH command code (10)

to CMD[1:0] signals. CMD[5:3] signals must be

driven with the index to the GMR pair for use in

this SEARCH operation. CMD[8:6] signals must

be driven with the same bits that will be driven

on SADR[21:19] by this device if it has a hit.

DQ[67:0] must be driven with the 68-bit data

([135:68]) to be compared against all even loca-

tions. The CMD[2] signal must be driven to logic

'0.'

– Cycle B: The host ASIC continues to drive the

CMDV high and applies SEARCH command

code (10) on CMD[1:0]. CMD[5:2] must be driv-

en by the index to the comparand register pair

for storing the 136-bit word presented on the DQ

Bus during Cycles A and B. CMD[8:6] signals

must be driven by the index of the SSR that will

be used for storing the address of the matching

entry and hit flag. The DQ[67:0] is driven with

68-bit data ([67:0]), compared to all odd loca-

tions.

Note: For 136-bit searches, the host ASIC must

supply two distinct, 68-bit data words on

DQ[67:0] during Cycles A and B. The even-

numbered GMR of the pair specified by the

GMR Index is used for masking the word in Cy-

cle A. The odd-numbered GMR of the pair spec-

ified by the GMR Index is used for masking the

word in Cycle B.

The SEARCH command is a pipelined operation

that executes searches at half the rate of the fre-

quency of CLK2X for 136-bit searches in x136-bit-

configured tables. The latency of SADR, CE_L,

ALE_L, WE_L, SSV, and SSF from the 136-bit

SEARCH command cycle (two CLK2X cycles) is

shown in Table 30, page 40.

The timing diagram for all SRAM interface signals,

SSV, and SSF shift to the right for different values

of TLSZ, as specified in Table 28, page 40.

In addition, SSV and SSF shift to the right for dif-

ferent values of HLAT, as specified in Table 29,

page 40.

The result of the SEARCH operation appears as

an SRAM READ Cycle with a pipelined latency. It

is specified as shown in Table 30, page 40.

Figure 27. Hardware Diagram for a Table with One Device (136-bit Operation)

DQ[67:0]

CMDV, CMD[8:0]

SSF, SSV

SRAM

LHO[1]

BHI[2:0]

LHI

3210

M7010R

LHO[0]

654

AI07040

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