M7010R datasheet(60/67 Pages) STMICROELECTRONICS

60 / 67 page

M7010R

60/67

SRAM WRITE. Enables WRITE access to the off-

chip SRAM containing associative data. The laten-

cy from the second cycle of the WRITE Instruction

to the address appearing on the SRAM bus is the

same as the latency of the SEARCH Instruction,

and will depend on the TLSZ value parameter pro-

grammed into the device configuration register.

Note: SRAM WRITE is a pipelined operation - new

instruction can begin right after the previous com-

mand has ended. The following explains the

SRAM WRITE operation accomplished through a

table of only one device with the following param-

eters: TLSZ = 00, HLAT = 000, LRAM = 1, and

LDEV = 1. Figure 44, page 61 shows the timing di-

agram. For the following description, the selected

device refers to the only device in the table as this

is the only device that will be accessed.

– Cycle 1A:The host ASIC applies the WRITE In-

struction on CMD[1:0] using CMDV = 1. The DQ

Bus supplies the address, with DQ[20:19] set to

“10,” to select the SRAM address. The host

ASIC selects the device for which the ID[4:0]

matches the DQ[25:21] lines. The host ASIC

also supplies SADR[21:19] on CMD[8:6] in this

cycle.

Note: CMD[2] must be set to '0' for SRAM

WRITE, because burst WRITES into the SRAM

are not supported.

– Cycle 1B: The host ASIC continues to apply the

WRITE InstructiononCMD[1:0] using CMDV =

1. The DQ Bus supplies the address with

DQ[20:19] set to “10” to select the SRAM ad-

dress.

Note: CMD[2] must be set to '0' for SRAM

WRITE, because burst WRITES into the SRAM

are not supported.

– Cycle 2: The host ASIC continues to drive

DQ[67:0]. The data in this cycle is not used by

the M7010R.

– Cycle 3: The host ASIC continues to drive

DQ[67:0]. The data in this cycle is not used by

the M7010R.

At the end of Cycle 3, a new command can begin.

The WRITE is a pipelined operation; however, the

WRITE cycle appears at the SRAM bus with the

same latency as the SEARCH Instruction (as mea-

sured from the second cycle of the WRITE com-

mand).

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