M7010R datasheet(34/67 Pages) STMICROELECTRONICS

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M7010R

34/67

SEARCH COMMAND

The M7010R Search Engine can be configured in

three ways:

1. 68-bit

2. 136-bit

3. 272-bit

4. Mixed-sized SEARCHES on tables config-

ured with different widths

68-bit Configuration

Figure 25, page 35 shows the timing diagram for a

SEARCH operation in the 68-bit-configured table

(one device only). This illustration assumes that

the host ASIC has programmed TLSZ to '00,'

HLAT to '000,' LRAM to '1,' and LDEV to '1' in the

command register. The hardware diagram for this

search subsystem is shown in Figure 24.

– Cycle A: Thehost ASICdrives CMDV highand

applies the SEARCH command code (10) on

CMD[1:0]. CMD[5:3] must be driven by the in-

dex to the global mask register pair for use in

the SEARCH operation. CMD[8:6] signals must

be driven by the same bits that will be driven on

SADR[21:19] by this device if it has a hit.

DQ[67:0] must be driven with the data to be

compared. CMD[2] signal must be driven to log-

ic '0.'

– Cycle B: The host ASIC continues to drive

CMDV high and to apply the SEARCH com-

mand (10) on CMD[1:0]. CMD[5:2] must be driv-

en by the index of the comparand register pair

for storing the 136-bit word presented on the DQ

Bus during Cycles A and B. CMD[8:6] signals

must be driven with the index of the SSR that

will be used for storing the address of the

matching entry and the hit flag. The DQ[67:0]

continues to carry the 68-bit data to be com-

pared.

Note: In the 68-bit configuration, the host ASIC

must supply the same data on DQ[67:0] during

cycles A and B. The even and odd GMR pairs

selected for the compare must be programmed

with the same value.

The SEARCH command is a pipelined operation

and executes a SEARCH at half their rate of fre-

quency of CLK2X for 68-bit searches in x68-con-

figured tables. The latency of SADR, CE_L,

ALE_L, WE_L, SSV, and SSF

from 68-bit

SEARCH Command cycle (= two CLK2X cycles)

is shown in Table 27, page 36.

The timing diagram for all SRAM interface signals,

SSV, and SSF shift to the right for different values

of TLSZ, as specified in Table 25, page 36 and Ta-

ble 26, page 36.

In addition, SSV and SSF shift to the right for dif-

ferent values of HLAT, as specified in Table 26,

page 36.

68-bit Configuration with LDEV = 1. The

de-

vice is configured to be the last in the depth-cas-

caded table by setting LDEV to '1' in the Command

the SSF and SSV signals in cycles when all up-

stream devices do not drive these signals. The

M7010R with its LDEV Bit set drives SSF and SSV

during a search with a miss or with non-search

commands (see the LDEV Bit definition in Table

10, page 20).

68-bit Configuration with LRAM = 1. Setting

LRAM to '1' in the Command Register configures

the device to be the last on the SRAM Bus. In a cy-

cle where the upstream device does not drive the

SRAM Bus, the last device of the SRAM Bus (with

LRAM = 1) drives the bus (SADR, CE_L, WE_L,

ALE_L) when they are active. When set to '1,' the

LRAM Bit sets the default driver for the SRAM con-

trol signals (SADR, CE_L, WE_L, and ALE_L).

Figure 24. Hardware Diagram for a Table with a Single Device (68-bit Operation)

DQ[67:0]

CMDV, CMD[8:0]

SSF, SSV

SRAM

LHO[1]

BHI[2:0]

LHI

3210

M7010R

LHO[0]

654

AI07040

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