M7010R datasheet(28/67 Pages) STMICROELECTRONICS

28 / 67 page

M7010R

28/67

READ COMMAND

TheREAD canbeasingleread of adataarray, a

mask array, an SRAM, or a register location

(CMD[2] = 0). It can be a burst READ (CMD[2] = 1)

using an internal auto-incrementing address regis-

ter (RBURADR) of the data or mask array loca-

tions (see Table 18, page 30 and Table 19, page

30 for formats).

A single-location READ operation takes six cycles,

as shown in Figure 20, page 29. The burst READ

adds two cycles for each successive read. The

SADR[21:19] bits supplied in the READ Instruction

Cycle A drives SADR[21:19] signals during the

PIO READ of an SRAM location.

The single READ operation takes six CLK cycles,

in the following sequence:

– Cycle 1: The host ASIC applies the READ In-

struction on the CMD[1:0] (CMD[2] = 0), using

CMDV = 1, and the DQ Bus supplies the ad-

dress, as shown in Table 19, page 30 and Table

20, page 30. The host ASIC selects the device

for which ID[4:0] matches the DQ[25:21] lines. If

DQ[25:21] = 11111, the host ASIC selects the

M7010R with the LDEV Bit set. The host ASIC

also supplies SADR[21:19] on CMD[8:6] in Cy-

cle A of the READ Instruction if the READ is di-

rected to the external SRAM.

– Cycle 2: The host ASIC releases the DQ[67:0]

bus to a tri-state condition.

– Cycle 3: The host ASIC keeps DQ[67:0] bus in

a tri-state condition.

– Cycle 4: The selected device starts to drive the

DQ[67:0] bus and drives the ACK signal from Z

to low.

– Cycle 5: The selected device drives the READ

data from the addressed location on the

DQ[67:0] bus and drives the ACK signal high.

– Cycle 6: The selected device floats the

DQ[67:0] bus and drives the ACK signal low.

At the termination of Cycle 6, the selected device

releases the ACK line to a tri-state condition. The

READ Instruction is complete, and a new opera-

tion can begin.

The burst READ operation lasts 4 + 2n CLK-cycles

(where “n” stands for the number of accesses in

the burst specified by the BLEN field of the RBUR-

REG) in the sequence shown in Figure 21, page

29. This operation assumes that the host ASIC

has programmed the RBURREG with the starting

address (ADDR) and the length of transfer (BLEN)

before initiating the burst READ command.

– Cycle 1: The host ASIC applies the READ In-

struction on the CMD[1:0] (CMD[2] = 1), using

CMDV=1 and the address supplied on the DQ

Bus, as shown in Table 21, page 31. The host

ASIC selects the device for which ID[4:0] match-

es the DQ[25:21] lines. If DQ[25:21] = 11111,

the host ASIC selects the M7010R with the

LDEV Bit set.

– Cycle 2: The host ASIC floats DQ[67:0] to a tri-

state condition.

– Cycle 3: The host ASIC keeps DQ[67:0] bus in

a tri-state condition.

– Cycle 4: The selected device starts to drive the

DQ[67:0] bus and drives ACK, and EOT from Z

to low.

– Cycle 5: The selected device drives the READ

data from the addressed location on the

DQ[67:0] bus and drives the ACK signal high.

Note: Cycles four and five repeat for each addi-

tional access until all the accesses specified in

the burst length (BLEN) field of RBURREG are

complete. On the last transfer, the M7010R

drives the EOT signal high.

– Cycle (4 + 2n): The selected device drives the

DQ[67:0] to 3-state condition and drives the

ACK and the EOT signals low.

At the termination of Cycle 4 + 2n, the selected de-

vice floats the ACK line to 3-state condition. The

burst READ Instruction is complete, and a new op-

eration can begin (see Table 21, page 31 for burst

READ address formats).

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