R5F572TFCDFB datasheet(8/120 Pages) RENESAS

8 / 120 page

R01DS0331EJ0110 Rev.1.10

Page 8 of 120

Oct 06, 2023

RX72T Group

1. Overview

Communication

function

Serial communications

interfaces (SCIj, SCIi,

SCIh)

 7 channels

SCIj: SCI1, SCI5, SCI6, SCI8, SCI9

SCIi: SCI11

SCIh: SCI12

 SCIj, SCIi, SCIh

Serial communications modes: Asynchronous, clock synchronous, and smart-card

interface

Multi-processor function

On-chip baud rate generator allows selection of the desired bit rate

Choice of LSB-first or MSB-first transfer

Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12

Start-bit detection: Level or edge detection is selectable.

Simple I2C

Simple SPI

7, 8, 9-bit transfer mode

Bit rate modulation

Double-speed mode

Data match detection (SCI12 is not supported)

Event linking by the ELC (supported by SCI5 only)

 SCIi Only

Capable of serial sending and receiving with 16-byte FIFO-buffered structure both at

transmission and reception sections

 SCIh Only

Supports the serial communications protocol, which contains the start frame and

information frame

Supports the LIN format

I2C bus interface (RIICa)

 1 channel

Communication formats

I2C bus format/SMBus format

Supports the multi-master

Max. transfer rate: 400 kbps

 Event linking by the ELC

CAN module (CAN)

 1 channel

 Compliance with the ISO11898-1 specification (standard frame and extended frame)

 32 mailboxes per channel

Serial peripheral

interface (RSPIc)

 1 channel

 RSPI transfer facility

Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),

and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four

lines) or clock-synchronous operation (three lines)

Capable of handling serial transfer as a master or slave

 Data formats

Switching between MSB first and LSB first

The number of bits in each transfer can be changed to any number of bits from 8 to 16,

20, 24, or 32 bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with each

frame having up to 32 bits)

Transmit/receive data can be swapped in byte units

 Buffered structure

Double buffers for both transmission and reception

 RSPCK can be stopped with the receive buffer full for master reception.

 Event linking by the ELC

Table 1.1

Outline of Specifications (7/9)

Classification

Module/Function

Description

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