R5F572TFCDFB datasheet(2/120 Pages) RENESAS

2 / 120 page

R01DS0331EJ0110 Rev.1.10

Page 2 of 120

Oct 06, 2023

RX72T Group

1. Overview

Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different

packages.

Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs

depending on the pin number on the package and the code flash memory capacity. For details, see Table 1.2,

Comparison of Functions for Different Packages.

Table 1.1

Outline of Specifications (1/9)

Classification

Module/Function

Description

CPU

 Maximum operating frequency: 200 MHz

 32-bit RX CPU (RXv3)

 Minimum instruction execution time: One instruction per state (cycle of the system clock)

 Address space: 4-Gbyte linear

 Register set of the CPU

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

 113 instructions

Standard provided instructions: 111

Basic instructions: 77

Single precision floating point instructions: 11

DSP instructions: 23

Instructions for register bank save function: 2

 Addressing modes: 11

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32 × 32 → 64 bits

 On-chip divider: 32/32 → 32 bits

 Barrel shifter: 32 bits

FPU

 Single-precision (32-bit) floating-point number

 Data types and floating-point exceptions in conformance with the IEEE754 standard

function

 Fast collective saving and restoration of the values of CPU registers

 16 save register banks

Memory

Code flash memory

 Capacity: 1 Mbyte, 512 Kbytes

 ROM cache: Operation of an 8-Kbyte instruction fetching cache can be enabled or

disabled (this is disabled by default).

While ROM cache operation is enabled:

- when the cache is hit, one-cycle access up to 200 MHz

- when the cache is missed:

one to two cycles if ICLK ≤ 120 MHz (bus wait: 0 cycles),

two to three cycles if ICLK > 120 MHz (bus wait: 1 cycle).

While ROM cache operation is disabled:

one cycle if ICLK ≤ 120 MHz (bus wait: 0 cycles),

two cycles if ICLK > 120 MHz (bus wait: 1 cycle).

 On-board programming: Five types

 Off-board programming (parallel programmer mode)

 The trusted memory (TM) function protects against the reading of programs from blocks

8 and 9.

Data flash memory

 Capacity: 32 Kbytes

 Programming/erasing: 100,000 times

Unique ID

 12-byte unique ID for the device

RAM

 Capacity: 128 Kbytes

 200 MHz No-wait access

 SED (single error detection)

RAM with ECC

 Capacity: 16 Kbytes

 00FF C000h to 00FF FFFFh (16 Kbytes)

 SEC-DED (single error correction/double error detection)

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