R5F572TFCDFB datasheet(80/120 Pages) RENESAS

80 / 120 page

R01DS0331EJ0110 Rev.1.10

Page 80 of 120

Oct 06, 2023

RX72T Group

2. Electrical Characteristics

Figure 2.29

Output Disable Time for POE in Response to the Simultaneous Conduction of Output

Pins

Figure 2.30

Output Disable Time for POE in Response to Detection of the Comparator Outputs

Figure 2.31

Output Disable Time for POE in Response to the Register Setting

Figure 2.32

Output Disable Time for POE in Response to the Oscillation Stop Detection

Outputs

disabled

Simultaneous active-level outputs detected*1

Note 1. When the active level is set to low.

MTU PWM output pins

GPTW PWM output pins

tPOEDO

COMPn level detection

signal (n = 0 to 5)

MTU PWM output pins

GPTW PWM output pins

Outputs disabled

tPOEDC

MTU PWM output pins

GPTW PWM output pins

Outputs disabled

tPOEDS

Corresponding bit in

the SPOER register

Oscillation stop detection

signal (internal signal)

MTU PWM output pins

GPTW PWM output pins

Outputs disabled

tPOEDOS

Main clock

R5F572TFCDFB 数据表(PDF) 80 Page - Renesas Technology Corp

R5F572TFCDFB 数据表(HTML) 80 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

R5F572TFCDFB 数据表(PDF) 80 Page - Renesas Technology Corp

R5F572TFCDFB 数据表(HTML) 80 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载