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PSD913F2 数据表(PDF) 77 Page - STMicroelectronics |
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PSD913F2 数据表(HTML) 77 Page - STMicroelectronics |
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77 / 94 page ![]() Preliminary Information PSD9XX Family 73 -12 -15 -20 Turbo Symbol Parameter Conditions Min Max Min Max Min Max Off Unit tLVLX ALE or AS Pulse Width 26 26 30 ns tAVLX Address Setup Time (Note 3) 9 10 12 ns tLXAX Address Hold Time (Note 3) 9 12 14 ns tAVQV Address Valid to Data Valid (Note 3) 120 150 200 Add 20 ns t SLQV CS Valid to Data Valid 120 150 200 ns RD to Data Valid 8-Bit Bus (Note 5) 35 35 40 ns t RLQV RD or PSEN to Data Valid 8-Bit Bus, 8031, 80251 (Note 2) 45 50 55 ns t RHQX RD Data Hold Time (Note 1) 0 0 0 ns tRLRH RD Pulse Width (Note 1) 38 40 45 ns tRHQZ RD to Data High-Z (Note 1) 38 40 45 ns tEHEL E Pulse Width 40 45 52 ns tTHEH R/W Setup Time to Enable 15 18 20 ns tELTL R/W Hold Time After Enable 0 0 0 ns tAVPV Address Input Valid to (Note 4) 33 35 40 ns Address Output Delay Read Timing (3 V Versions) Microcontroller Interface – PSD9XXFV AC/DC Parameters (3 V Versions) NOTES: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals. 2. RD and PSEN have the same timing for 8031. 3. Any input used to select an internal PSD813F function. 4. In multiplexed mode latched address generated from ADIO delay to address output on any Port. 5. RD timing has the same timing as DS, LDS, and UDS signals. |
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