PSD913F2 datasheet(55/94 Pages) STMICROELECTRONICS

55 / 94 page

Preliminary Information

PSD9XX Family

The

PSD9XX

Functional

Blocks

(cont.)

9.4.6 Port C – Functionality and Structure

Port C can be configured to perform one or more of the following functions (see Figure 21):

t MCU I/O Mode

t PLD Input – Input to the PLDs.

t Address In – Additional high address inputs using the Input Micro

⇔Cells.

t In-System Programming – JTAG port can be enabled for programming/erase of the

PSD9XX device. (See Section 9.6 for more information on JTAG programming.)

Pins that are configured as JTAG pins in PSDsoft will not be available for other I/O

functions.

t Open Drain – Port C pins can be configured in Open Drain Mode

t Battery Backup features – PC2 can be configured as a Battery Input (Vstby) pin.

PC4 can be configured as a Battery On Indicator output

pin, indicating when Vcc is less than Vbat.

Port C does not support Address Out mode, and therefore no Control Register is required.

Pin PC7 may be configured as the DBE input in certain microcontroller interfaces.

9.4.7 Port D – Functionality and Structure

Port D has three I/O pins. See Figure 22. This port does not support Address Out mode,

and therefore no Control Register is required. Port D can be configured to perform one or

more of the following functions:

t MCU I/O Mode

t GPLD Output – Combinatorial PLD output (external chip selects)

t PLD Input – direct input to PLDs

t Slew rate – pins can be set up for fast slew rate

Port D pins can be configured in PSDsoft as input pins for other dedicated functions:

t PD0 – ALE, as address strobe input

t PD1 – CLKIN, as clock input to the PLD and APD counter

t PD2 – CSI, as active low chip select input. A high input will disable the

Flash/SRAM and CSIOP.

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