PSD913F2 datasheet(31/94 Pages) STMICROELECTRONICS

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Preliminary Information

PSD9XX Family

The

PSD9XX

Functional

Blocks

(cont.)

9.1.1.9.4 Reset Pin Input – PSD934F2, PSD954F2

The reset pulse input from the pin will abort any operation in progress and reset the Flash

memory to Read Mode. When the reset occurs during a programming or erase cycle, the

Flash memory will take up to 25 µsec to return to Read Mode. It is recommended that the

reset pulse (except power on reset, see Reset Section) be at least 25 µSec such that the

Flash memory will always be ready for the MCU to fetch the boot codes after reset is over.

9.1.2 SRAM

The SRAM is enabled when RS0— the SRAM chip select output from the DPLD— is high.

RS0 can contain up to two product terms, allowing flexible memory mapping.

The SRAM can be backed up using an external battery. The external battery should be

connected to the Vstby pin (PC2). If you have an external battery connected to the

PSD9XX, the contents of the SRAM will be retained in the event of a power loss. The

contents of the SRAM will be retained so long as the battery voltage remains at 2V or

greater. If the supply voltage falls below the battery voltage, an internal power switchover

to the battery occurs.

Pin PC4 can be configured as an output that indicates when power is being drawn from the

external battery. This Vbaton signal will be high with the supply voltage falls below the bat-

tery voltage and the battery on PC2 is supplying power to the internal SRAM.

The chip select signal (RS0) for the SRAM, Vstby, and Vbaton are all configured using

PSDsoft.

9.1.3 Memory Select Signals

The main Flash (FSi), Secondary Flash (CSBOOTi), and SRAM (RS0) memory select

signals are all outputs of the DPLD. They are setup by entering equations for them in

PSDsoft. The following rules apply to the equations for the internal chip select signals:

1. Main Flash memory and Secondary Flash memory sector select signals must not be

larger than the physical sector size.

2. Any main Flash memory sector must not be mapped in the same memory space as

another Main Flash sector.

3. A Secondary Flash memory sector must not be mapped in the same memory space as

another Secondary Flash sector.

4. SRAM, I/O, and Peripheral I/O spaces must not overlap.

5. A Secondary Flash memory sector may overlap a main Flash memory sector. In case

of overlap, priority will be given to the Secondary Flash sector.

6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority

will be given to the SRAM, I/O, or Peripheral I/O.

Example

FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from

8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0

will always access the SRAM. Any address in the range of CSBOOT0 greater than 87FFh

(and less than 9FFFh) will automatically address Boot memory segment 0. Any address

greater than 9FFFh will access the Flash memory segment 0. You can see that half of the

Flash memory segment 0 and one-fourth of Boot segment 0 can not be accessed in this

example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to

BFFFh would not be valid.

Figure 5 shows the priority levels for all memory components. Any component on a higher

level can overlap and has priority over any component on a lower level. Components on

the same level must not overlap. Level one has the highest priority and level 3 has the

lowest.

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