SBPH400-3 datasheet(30/43 Pages) STMICROELECTRONICS

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SBPH400-3

Figure 2.16

PHY/Link interface start-up timing

When LPS is reasserted, the SBPH400 resumes sending SCLK (if necessary) after 40-60 ns

if the SBPH400 is operational, or otherwise after a nominal period of 500

µsec if LPS is used

to bring the SBPH400 out of suspend. If the interface is operating in direct mode (ISO = 0) then

Ctl[0:1] and D[0:7] are held zero. If the interface is operating in isolated mode (ISO = 1), then

the SBPH400 maintains high impedance for the first cycle of SCLK, asserts zeros on Ctl[0:1]

and D[0:7] for the second cycle of the resumed SCLK, and maintains high impedance for

cycles 3 to 7. The SBPH400 asserts a nominal receive indication on Ctl[0:1] for the eigth cycle,

while simultaneously indicating data_prefix on D[0:7] (all 1’s). This is maintained for further

cycles if the SBPH400 is in a state where it would otherwise be transferring data.

2.9.3 PHY/Link interface reset and disable

The PHY-Link interface may be reset by taking LPS low for a minimum of 2.75

µsec, but less

than 25

µsec. During this time the Ctl[0:1] and D[0:7] signals are disabled, but the SBPH400

continues to provide SCLK.

If neither of these is true for a period greater than 25

µsec, then no signal is considered to be

received on LPS, the link interface is disabled, and the SBPH400 operates as a PHY repeater.

When the link interface is disabled, all outputs are held to zero if the interface is operating in

direct mode (ISO = 0), otherwise (ISO = 1) all outputs are maintained in high impedance. The

LP S

SC lk (d ir ect)

SC lk (is o)

C [0:1], D[0:7 ]

(iso )

(dire ct)

5n s (m in)

40 - 6 0 n s (S BP H 400 op era tio na l)

50 0

µs nom inal (SBPH400 suspended)

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