SBPH400-3 datasheet(39/43 Pages) STMICROELECTRONICS

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SBPH400-3

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Table 5.2

AC characteristics (digital interfaces)

Symbol Parameter

Measured

Condition Unit

Min

Typ

Max

tpsu

D, CTL, LREQ input setup to SCLK

output

50% to 50%

tph

D, CTL, LREQ hold from SCLK output 50% to 50%

tlsu

D, CTL output setup to SCLK

50% to 50%

6.5

tlh

D, CTL output hold from SCLK

50% to 50%

0.5

td1

Delay time, SCLK input high to initial

instances of D, CTL and LREQ

outputs valid

50% to 50%

td2

Delay time, SCLK input high to

subsequent instances of D, CTL and

LREQ outputs valid

50% to 50%

td3

Delay time, SCLK input high to D, CTL

and LREQ outputs invalid (tri-state)

50% to 50%

Table 5.3

Clock and reset parameters

Symbol Parameter

Measured

Condition Unit

Min

Typ

Max

Fextclk

External clock Frequency

24.576 MHz +/- 2.45 KHz

Dextclk

External clock duty cycle

50% to 50%

45%

55%

Jextclk

External clock Jitter peak to peak

100 pS peak to peak

FSCLK

SCLK frequency

50% to 50%

Fextclk

× 2

DSCLK

SCLK duty cycle

50% to 50%

45%

55%

Power-on reset time, RESET# input

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