LP1071 Advance Information, Rev. 0.5

4

Freescale Semiconductor

PRELIMINARY

Functional Description

3

Functional Description

Figure 1 is a functional block diagram of the LP1071, which is divided into three main subsystems.

Figure 1. Functional Block Diagram

3.1

Embedded Processor Subsystem

The embedded Processor Subsystem consists of the following:

•

An embedded ARM7TDMI microprocessor running at 88 MHz

•

An ARM® Peripheral Subsystem accessed via an extended APB (APB+) bus

3.1.1

UART

The UART is used for testing and diagnostic purposes and is capable of supporting data transfer rates of

up to 115.2 kbps.

Semiconductor Technology

0.18 micron

RF Support

Airoha, Maxim

Certification

Wi-Fi® (incl. WPA), WQHL, FCC Part 15

Table 1. Specifications (continued)

Feature

Details

ARM7TDMI

Bridge

Interrupt

Controller

SDIO

Registers

UART

JTAG

EEPROM

Interface

GPIO

Memory

Controller

On-Chip

RAM/ROM

ARM

Subsystem

Clock

Control

PLL

Watchdog

Timer

I/Q ADC

I/Q DAC

Aux ADC

Aux DAC

RSSI

ADC

AFE

ARM

Interface

AFE

Control

MAC-PHY

Interface

Clock Select

Logic

WEP

Engine

AES

Engine

Shared

Memory

Controller

Shared

Memory

ARM

Interface

AHB

AHB

Generic

Host

Interface

DMA

MAC Subsystem

PHY

Subsystem

SDIO

Interface

Protocol

Accelerator

Subsystem

RMB

Registers

Clock

Gating

802.11

Protocol

Accelerator

LP1071 Chip Boundary

CLKIN

(From TCXO)