Functional Description

LP1071 Advance Information, Rev. 0.5

Freescale Semiconductor

5

PRELIMINARY

3.1.2

JTAG

TBA

3.1.3

Serial EEPROM Interface

The LP1071 supports an external serial EEPROM for storing the boot loader, MAC address, calibration

data and any other vendor-specific data. The LP1071 supports serial EEPROMs of sizes from 8 Kbit

(organized as 1024 entries of 8 bits each, or 1024 x 8) up to 512 Kbit (organized as 65,536 x 8). Serial

EEPROMs from the following vendors have been tested and verified to work with the LP1071:

•

ATMEL (http://www.atmel.com)

•

ST Microelectronics (http://www.st.com)

•

Microchip Technology (http://www.microchip.com)

•

Catalyst Semiconductor (http://www.catsemi.com)

•

Integrated Silicon Solutions, Inc. (http://www.issi.com)

serial EEPROMs.

The operating frequency of the serial EEPROM port is 400 kHz with a supply voltage of 3.0 V.

3.1.4

GPIO

To support vendor-specific needs, the LP1071 provides eight bi-directional General Purpose Input Output

(GPIO) pins. Each pin can be independently configured as an input, output or an interrupt source. On reset,

the GPIOs default as inputs, i.e. output drivers enables will be inactive.

3.1.5

RMB Registers

This block contains all the reset logic for both CPUs contained in the BRC and chip-wide reset control. It

also defines controls for memory address re-mapping.

3.1.6

Watchdog

TBA

3.1.7

Interrupt Controller

TBA

3.1.8

SDIO Registers

TBA