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LP1071 数据表(PDF) 18 Page - Freescale Semiconductor, Inc |
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LP1071 数据表(HTML) 18 Page - Freescale Semiconductor, Inc |
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18 / 32 page  LP1071 Advance Information, Rev. 0.5 18 Freescale Semiconductor PRELIMINARY Pinout and Footprint Clocks and Resets and Mode EMBEDDED_RESET_N pdisdgz input Embedded board reset E10 PLL_BYPASS pdidgz input Bypass the internal PLL and use PLL_BYPASS_CLK A9 PLL_BYPASS_CLK pdidgz input PLL bypass clock input A10 AVDD_PLL pdiana2p N/A Analog 3.3 volt D2 AVSS_PLL pdiana2p N/A Analog ground D1 TAVDDPOWER pvdd3p N/A 3.3 volt power for ESD Diodes E3 TAVssPOWER pvss3p N/A 3.3 volt power for ESD Diodes A3 DVDD_PLL pdiana2p N/A 1.8 volt digital power for PLL F3 DVSS_PLL pdiana2p N/A 1.8 volt digital ground for PLL E2 TXCO_BYPASS pdidgz input Bypass the TCXO and use the TCXO_BYPASS_CLK B10 TXCO_BYPASS_CLK pdidgz input TCXO bypass clock A11 XTAL_BYPASS pdidgz input Bypass the XTAL oscillator and use the XTAL_BYPASS_CLK D11 XTAL_BYPASS_CLK pdidgz input XTAL bypass clock C12 FAST_CLK_POWER pdo02cdg output Enable the TCXO B9 XTAL_32K_XIN pdxoe4dg analog 32 kHz crystal (NOTE: Must be placed next to PVDD1DGZ.) B12 XTAL_32K_XOUT analog 32 kHz crystal B11 RESET_N pdisdgz Input Chip Reset D10 CHIP_MODE0 pdidgz Input Chip Mode Select G3 CHIP_MODE1 pdidgz Input Chip Mode Select H2 CHIP_MODE2 pdidgz Input Chip Mode Select H1 CHIP_MODE3 pdidgz Input Chip Mode Select H3 JTAG JTAG_RESET pdudgz Input Tap reset L7 JTAG_CLOCK pdisdgz input Tap clock L8 JTAG_DI pdudgz input Tap data in M8 JTAG_DO pdo02cdg output Tap data out K8 JTAG_MODE pdudgz input Tap Mode K9 ARM Sub-system Signals ARM_GPIO0 pdb04dgz bi-dir General Purpose I/O M2 ARM_GPIO1 pdb04dgz bi-dir General Purpose I/O L3 ARM_GPIO2 pdb04dgz bi-dir General Purpose I/O K4 ARM_GPIO3 pdb04dgz bi-dir General Purpose I/O L4 Table 9. Pin Description (continued) Pad Name Pad Type Direction Description Pin |
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