LP1071 datasheet(12/32 Pages) FREESCALE

12 / 32 page

LP1071 Advance Information, Rev. 0.5

Freescale Semiconductor

PRELIMINARY

LP1071 Interfaces

Table 8. SDIO Function 1 Registers

Bit

Name

Description

ARM

Access

HOST

Access

Reset

Watchdog Status Register (offset 0x000E)

Wdog_reset

This is a read only bit that when ‘1’ indicates that

the LP1071 ASIC has had a watchdog reset

occur.

7:1

Reserved

—

SDIO Host to Device Interrupt request register 0 (0x000F)

7:0

Write_sdio_arm_int

Each bit in this register is 1 of 8 ARM interrupt

requests from the SDIO Host to the device ARM.

The Host should request an interrupt by writing a

“1” to the corresponding bit in this register. The

the register. Once the ARM has cleared the

“0” again.

—

0’s

Device to SDIO Host Interrupt Source register 0 (0x0013)

7:0

Arm_to_sdio_int_clr[7:0] for

writes.

Arm_to_sdio_int_src[7:0] for

reads.

This register contains the interrupt pending status

of the SDIO Host interrupt from the device. The

device is capable of generating up to 8 individual

requests. Each bit in this register is ANDed with

the corresponding ARM to SDIO Host Interrupt

enable register. The ANDed bits are then ORed

together to generate a single SDIO Host interrupt

in the cccr register space. To clear a particular

interrupt bit the SDIO Host should write a “1” to

that particular bit in this register.

—

0’s

Device to SDIO Host Interrupt Source register 1 (0x0014)

2:0

Arm_to_sdio_int_clr[10:8] for

writes.

Arm_to_sdio_int_src[10:8]

for reads.

This register contains the interrupt pending status

of the SDIO Host semaphore 0-2 host granted

indication. When the Host requests a semaphore

the corresponding interrupt will be triggered when

the host has been granted the interrupt. Bit 0 is

semaphore 0; bit 1 is semaphore 1; and bit 2 is

semaphore 2. Each bit in this register is ANDed

with the corresponding ARM to SDIO Host

Interrupt enable register. The ANDed bits are then

ORed together to generate a single SDIO Host

interrupt in the cccr register space. To clear a

particular interrupt bit the SDIO Host should write

a “1” to that particular bit in this register.

—

0’s

7:3

Reserved

—

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